myRIO sinusoid frequency errors

Hello

I have a big problem when generating a sinusoidal signal. I use core FPGA with an Express VI to generate the sinusoidal signal and tuned frequency is not the same result when I measured with an oscilloscope. For example, at 100 Hz out 119Hz; to 1000 Hz is released 1200Hz and 5000Hz was released 5800Hz.

Please I need help as soon as possible for my graduate studies.

the entrance to the generator sine takes a + 32.0.  your code did not provide the full 32 bits, and the result was no frequency of course.

I have attached a version update.  This should work much better.  as I have noted in VI, I do not generally the calculation of the increase of the FPGA code generation.  This calculation is usually in floating-point in RT code.  But if you need it in FPGA, then, it's a way to do.

Tags: NI Products

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