Generation of sinusoid frequency accurate FPGA

Hello everyone,

I have a myRIO and I want to build a lock in the amplifier. To this effect, I need excite (in fact the driver laser) laser with a certain frequency, in a case 32754 + to 1 Hz. This signal must be a square wave. I need a sine and a cosine with the excact same frequency that I use to turn on the laser. But the sine and cosine do not have to be sent outside the FPGA through a port analog or digital.

To summarize, I have need of a square wave, sine and cosine with excactly the same frequency. Only the square wave is sent through an analog port. (I use the "square wave generation.vi")

This works very well for example 4212 Hz. But 32754Hz can't be represented pretty good by a 40 MHz clock (a lot of jitter). To this effect, I thought to use a Schmitt Trigger.

Finally I come to the point! I use the "generator.vi of sine wave' on the FPGA.

Can I output a sine wave signal with any frequency I want to use this VI, if right of Nyquist is hurt? As this VI uses DDS I think that Yes, can anyone confirm this?

I only ask, because the sine wave will be converted into a square by the schmitt trigger signal and should always have the same frequency that it represents in the FPGA.

Kind regards

Slev1n

Slev1n wrote:

Hey, JLewis,.

1, how can I calculate/derive the resolution?

2, the size of the LUT or also the resolution of the amplitude of the a influence on the resolution of frequency?

1. the resolution only depends on the accumulator and clock rate, e.g. 40 MHz / 2 ^ 32. The rate of the clock increases the resolution of the average frequency of DDS, but will negatively affect the jitter due to the clock period. In your case, it seems that you are more interested in the resolution of frequencies without jitter, which are those for which the clock frequency is an integer multiple of the frequency, for example freq * k = 40 MHz. You can play games with clocks derived from hitting a specific frequency, but in general most of the frequencies will be free of jitter.

2. the other settings do not affect the resolution, but affect the phase noise and/or quantification. For your application, I expect that phase noise is the biggest problem and is affected by the LUT, the interpolation option size and samples/cycle (IE, the rate of the loop). Quantization noise is affected by the output data type and amplitude (otherwise the range). You will get a filtering via the D/A conversion and the Schmitt trigger, so it is difficult to predict how much of a concern these parameters will be for you.

You can see the Xilinx DDS generator (on the pallets of Xilinx IP integration). He has a few more options as the dithering phase and a 48-bit accumulator. On the theory and the effects of various parameters of their documentation is excellent: http://www.xilinx.com/support/documentation/ip_documentation/dds_compiler/v6_0/pg141-dds-compiler.pd...

I hope this helps!

Tags: NI Software

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