PPS and timekeeper FPGA

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• Typical time a request for interruption takes between RT LV and LV FPGA.

  Currently, I don't have the equipment to test it, and I was looking for some statistics calendar all the time it takes for a request for interruption to process between LV RT and FPGA LV (LV RT generate the interrupt request, waiting LV RT on ack, LV FPGA get query pause and LV FPGA ack, LV RT continue).  I know that the interrupt request has a priority higher loop timed on LV RT, and a concern for this issue, let me say that the FPGA LV does not what whatsoever between the receipt of the interrupt request and receipt.

  Does anyone have any time?

  Hello Michel_Gauvin,

  I found the following article in the knowledge base that may answer your questions:

  Landmarks of Module time real LabVIEW for Applications in the LabVIEW FPGA Module

  I hope this helps!

  Kind regards

• Drivers Xilinx/Multisim and Labview FPGA

  Where can I find drivers for my FPGA OR if I use Multisim/Xilinx and NOT of Labview?  All the links I found are Labview be installed.  However, the explicit manual FPGA indicates that you can use Multisim/XIlinx ISE in place.

  OK, I tested just outside. The Driver of LabVIEW 2013 DEFB contains 2 separate components, the driver and Module FPGA support. If you run this installer, it won't check if you have LabVIEW FPGA installed unless you check the box for LabVIEW FPGA support.

  I can change the text in the Installation Instructions to read "LabVIEW FPGA 2013 is required to install the LabVIEW FPGA Module Support component installation".

• FPGA VeriStand personality is late? and latent FPGA data processing

  I use a FPGA 7853 (only) in a SMU 1071 chassis with a controller 8135 and run VeriStand 2013 SP1.  At the end of my test, I want to ensure the integrity of the test, which includes the audit of the FPGA interface is never late.

  I first thought to expose the terminal 'Is?' late as a channel, but then I noticed it isn't really an account, it's just a flag.  In addition, it seems that this flag is not locked, it does report by iteration of loop interface.  This makes me think that I alarm an VeriStand on the later is for VeriStand FPGA interface design? channel.  Am I correct, and if not, how NOR have I use East late? terminal?

  As the DMA in the FPGA nodes then never expire, there no sense watching the Timed Out? terminals on the FPGA.  But the effect of a timeout will appear in the East towards the end? Terminal Server.  I'm tempted to change the end is? U64 to a real number in the number of late? the defined indicators synchronize to the host VI.  is there a reason to not do this?

  How VeriStand manages a FPGA end?  If the RT side of the DMA buffer became more complete, data from the FPGA would be more latent, which could lead to the instability of the system.  Hopefully the VeriStand engine should purge the latency of the data, but I don't see anything in the FPGA interface which would facilitate this.

  Thanks for your help,

  Steve K

  Hey Steve,

  If the PCL NIVS reads this flag as true, it incrememnts the County of HP system channel.

  For the question of FIFO depth: The PCL is always expected to read and write a # fixed packages each iteration (as defined by the XML) and FPGA always reads and writes the same number of packets of each loop of comm iteartion and since the timeout is set to-1... orders may not be combined. Packets act as a handshake.

• No option to simulate the peripheral cRIO after installing Labview and RT/FPGA Modules of downloads (lack of driver support?)

  Hi guys -.

  Basically, I need to simulate a cRIO device without yet having equipment on-site, like this:

  How to simulate the FPGA hardware target using with LabVIEW Project Explorer

  Instead, I only get the options presented in the attachment "Add Target Options.jpg.  I guess it's because of missing drivers, which I assume is due to an error that I made during a recent new LV installation installation went like this: I downloaded (not diskettes) and installed the following (in this order, the latest versions all around):

  (1) LabView development system

  (2) real-time module

  (3) FPGA module

  (4) NEITHER-RIO (previous installation-by-installation)

  (5) DAQmx

  At the end of (1) and (2), I got the screen shown in the second attachment ("Drivers Installer Message.jpg"), but could not able to recognize the folder "device drivers OR" (I also downloaded), or one of its subfolders.

  According to me, I'm missing an obvious option to load the necessary drivers after installation, but can't seem to find reference to it in the forums.  Could someone give me a little help in the right direction?

  Thanks a lot and have a nice day.

  
  

• difference between the real time module and module fpga

  Hi experts,

  I was wondering if someone could tell me the difference between the FPGA and the module in real time (in short).

  My understanding is that the FPGA module facilitates code LV that can then be designed for the specific advice of RIO, I have used this a bit in the past.

  The real time module, I'm a little more unsure about, all I know is that it allows the creation of a 'real time' i.e. deterministic environment.

  My request is this: I wish I had several control loops running on two tables of RIO, with the host PC mainly used for recording data and user interface. I see that I have no need of RT on the host (Win XP should be good).

  Do I need the RT module?

  You are right.  In the scenario you describe, you won't need to LabVIEW RT. LabVIEW RT is used to create a deterministic execution on specific targets for intel such as the PXI-8106 and PXI-8108.  You can still use strings and floating point on RT.

• Problem with the combination of LabVIEW (dynamic distribution) classes, statechart module and module FPGA

  LOCATION:

  -I am developing a software plugin based on plug-ins based on LabVIEW classes that are instantiated in running. Plugin real classes come from the plug in generic classes that define interfaces to the VI instantiation and can provide basic functionality. This means that many of the methods of the class are dynamic distribution and even methods of child classes can call the parent method.

  -Plugins top level (the ones directly accessible by the main VI) each have a run method that animates a plug-in specific state transitions.

  -Transitions of the plug-in data acquisition (DAQ class) class calls a method of the DAQ class that reads data from an FPGA card OR and transmits to another component via a queue.

  PROBLEM:

  -Higher sampling rate, a FPGA-to-host FIFO overflow occurs after some time. When I "weigh" the system just by moving a window of Firefox browser on the screen, the overflow is triggered immediately. I did not have this kind of problem in older software, where I was also reading a FIFO of FPGA, but made no use of LabVIEW classes or diagrams.

  SOLUTIONS I'VE TRIED (WITHOUT SUCCESS):

  -J' put the transitions in a timed (instead of a simple while loop) loop that I assigned specifically to an own kernel (I have a quad-core processor), while I left all the other loops of my app (there many of them) in any simple loops. FIFO overflow still occurs, however.

  QUESTION:

  -Does anyone have a tip how I could fix this problem? What could be the cause: dynamic distribution methods, the acquisition of data of state transitions or just the fact that I have a large number of loops? However, I cannot change the fact that I have dynamic distribution methods because it is the essence of my architecture...

  Tips are greatly appreciated!

  I've now changed the execution priority of all the screws involved in reading of the FPGA FIFO '(highest) priority critical time '. This seems to be improving the situation much: so far I have not a FIFO overflow, even when I move around the windows on the screen. I hope it stays like that...

• Spartan - 3 driver and Labview FPGA 2009

  Hello

  Do we need a new Spartan-3E driver to work with Labview FPGA 2009? And, if so, is it provided by National Instruments?

  Thank you

  Walid F. van

  Hello everyone

  The driver for the Spartan 3rd WHAT XUP Starter Kit are now on the site OR here:

  http://digital.NI.com/express.nsf/bycode/Spartan3E?OpenDocument&lang=en&node=seminar_US

  Just click on the link to get driver.

  Kind regards

  John Harvey

• Two time of different loop and each FPGA implementation

  Hi, experts LV!

  I wondered that two different loops in the FPGA are possible to implement with the speed of each loop.

  Ex) SCTL and While loop in a same FPGA VI

  SCTL = 1 vs tick while loop graduations 43 (execution of the loop)

  Also, is it possible to transfer the T/F of SCTL signal any loop in a same FPGA VI via a local variable, even if they run different as loop above speeds?

  Yes you can.  Rather than ask, you might have just tried.  It would have been much faster for you.

• What are the differences between LabVIEW and LabVIEW FPGA and LabVIEW RT

  I need a comparison of LabVIEW, LabVIEW FPGA, and LabVIEW RT

  Sorry, I misunderstood.

  LabVIEW RT (LabVIEW Real-time) combines graphical LabVIEW of programming with the power of a real-time operating system, allowing you to create applications in real time.

• DMA between host and target FPGA is not supported for this remote system.

  I try to cover with my FPGA (on the cRIO-9002) of the RTO.  I have install upward of anOpen good VI reference without error, but as soon I try to access thefifo I error-63001 and the attached message wrote:

  Error-63001 occurredat reference FPGA VI opened in the target - multi rate - variables - fileIO_old.vi

  Possible reasons:

  NOR-RIO FPGACommunications framework: (Hex 0xFFFF09E7) DMA from the host to the FPGA targetis not supported for this remote system. Another method for controller of e/s or climatiqueLes associated with the FPGA target.

  What other I/O optionsdo I need to move the data asynchronously to the RTO for the FPGA. I have triedcreating memory, but it seems that I can't write to the memory of the RTOSside.

  We have also a 9012sitting around will using this cRIO rather solve this problem.

  I'm very very greenwhen it comes to LabView, so I apologize if this is an easy question.

  As stated in the readme of the driver NOR-RIO, DMA is not taken in charge from the host to the FPGA on the cRIO-900 x series. The cRIO-901 x supports DMA transfers between host and FPGA and FPGA to host all the cRIO-900 x series controllers only support transfers the FPGA host DMA. As a result, LabVIEW returns an error if you try to transfer using DMA controller for cRIO-900 x.

  The 9012 looks like the ideal solution, you are very lucky to have additional hardware laying around

• Cannot open .pps and .doc attachments in Windows Live Mail. OS = Windows 7 Asus computer notebook 64-bit

  I am able to open .pps laptop spare 'Windows 7' on my desktop computer, but can not open on Asus 64-bit of Windows Live Mail with the same e-mail software and OS

  PROBLEM SOLVED

  THANKS FOR THE HELP FROM AN EXPERT!

  Right-click | Save as. Appears in your folder list. Click Desktop and save.

  You can save anywhere you want to, I just thought it would be easier.

  Now this PP viewer's default, they should open the email. If they are not, then see this.

  Cannot open. PPS directly from Windows Mail or Windows Live Mail attachments
  http://www.Winhelponline.com/blog/unable-to-open-PPS-ppt-from-Windows-mail-or-WLM/

• With PPS and other wireless... why, son

  How to listen to the music on some of my PPS!

  WINDOWS 7.P.C.  fixed. In my list of slideshow PPS, all food but many play the music. They all have the same properties.

  I have downloade Viewer Microsoft PowerPoint 2007 and when I ask open with: there is no mention of PowerPoint Viewer , only Microsoft Power Point (original). So the problem persists.

  and Movie Maker... .me gives... .he misses... the dll system error.  I got fixed and said repairs continued and Movie Maker doesn't s, still not open.

  Help me, thanks.

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• Windows 8 and Labview FPGA 2013

  I installed Labview 2013 including the suite of FPGA design on a host Windows 8 (x 64). I was surprised to see Windows 8 on supported OS list that I did not know until this day no further action taken design Xilinx support Windows 8.

  But as a question of fact, that he did not long until I hit:

  ERROR: Failure of Simulator: 861 - link design

  following this tutorial by clicking the syntax check (using one of the files provided with the tutorial VHDL). The error is clearly linked to a lack of compatibility of Windows 8 from XIlinx running under Tools. Is there a known workaround solution? Thank you.

  Unfortunately, you cannot compile the code on a Windows 8 FPGA Xilinx still not having this compatibility. The KnolwedgeBase article describes it. There is also a link in this article to another article that describes how to compile your code on a remote computer. This is the preferred method to compile when you have a Windows 8.

  http://digital.NI.com/public.nsf/allkb/8FDE6923DA3C069786257A36005C3EEF?OpenDocument

• Independent of the 40 MHz clock Onboard FPGA PPS GPS meter

  Could you give me some advice or point me in the right direction?

  I need to time counter accurate/tick synchronized by GPS PPS synchronization signal.

  I got cRIO S.E.A. GPS Module that trigger PPS signal at the bottom of basket FPGA. PPS rising edge signal precisely mark the beginning of the second.

  When I measure the number of ticks of 40 MHz clock FPGA embedded in a (PPS) second number of ticks is not 40.000.000 ticks but something like 39,999,800 ticks.

  I want to measure with precision time between edges up/down digital signals. Because the clock of 40 MHz FPGA are drifting I can't use it.

  How could set up my own witch counter ticks will be put away with signal GPS PPS?

  I don't expect that I could provide 40 MHz FPGA on board the oscillator.

  Should I create my own counter which will increase the opposite by the value 1.000,005 (40 000 000 / 39,999,800) each tick and this counter will be running timed loop (chronometric 40 MHz FPGA embedded base). Increment the value (1,000...) will be updated every seconds dependent PPS vs FPGA clock drift.

  My configuration: cRIO-9025, cRIO-9116, S.E.A. GPS + cRIO module, high-speed DIs NI 9402, RT/FPGA LabVIEW 2011

  Looking forward to your hearing you.
  Peter

  Hi all

  This could help you.

  Timekeeper FPGA

  • http://digital.NI.com/public.nsf/allkb/EFDC35727D4F2CC086257A0700693003
  • https://decibel.NI.com/content/projects/NI-TimeSync-FPGA-timekeeper

  (I do not understand how this could be released on 23/05/2012)