SCTL FPGA flow and ready for input management

I studied the FPGA Normalize vector LV examples and I have a question on the loan for wire entry (see the attachment for the diagram).

A Subvi (named ReadyForInputLogic) is used to generate a ready for the true input signal each 7 cycles after each valid entry.

I understand the purpose of this sub - VI but it's the Subvi can be replaced by a wire between the 'ready for the entry' exit last ditch block and case diagram where the FIFO is read?

I also studied the example of co-processing FFT and there is no need to use this kind oh Subvi:

I modified this example to add some multiply and divide blocks after the block of the FFT. Thus, the flow of any new is increased to 8 cycles/sample (the block of the FFT is not the bottleneck).

I have to add the ReadyForInputLogic.vi in my SCTL Subvi read FIFO each 8 cycles?

Thanks a lot for any explanation

Zoomzoomzoom wrote:

RUFNEK wrote:

I understand the purpose of this sub - VI but it's the Subvi can be replaced by a wire between the 'ready for the entry' exit last ditch block and case diagram where the FIFO is read?

Yes you can, but then you run the risk of dropping a result when writing to the FIFO fails, because it is full. The logic is currently configured to stop processing vectors until the FIFO is not full.

RUFNEK wrote:

I modified this example to add some multiply and divide blocks after the block of the FFT. Thus, the flow of any new is increased to 8 cycles/sample (the block of the FFT is not the bottleneck).

I have to add the ReadyForInputLogic.vi in my SCTL Subvi read FIFO each 8 cycles?

Thanks a lot for any explanation

You must add the latencies to determine how many times you can read FIFO. The FFT under Setup for this example has a latency of > 5600 cycles before the output is valid.


I would say yes, because the FIFO will be ready for a new sample before your math blocks.

Tags: NI Software

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