Similar Questions

• Timed loop continues to turn after stop

  Only, I have seen this time, but thought I should ask about it.  After pressing the stop button, I was surprised that the diagnostic LED on the front panel of the main vi kept flashing.  With the performance highlighting ONE values showed that the timed loop was still running.  I checked the other 8 loops clocked subvis and they also ran. None of the methods Stop worked. Only stop LV and abandonment of the cRIO eliminated the problem.

  Run LV2014 SP1 on cRIO-9067 with dual-core ARM processor.  Windows 7 x 32.

  BTW: The function of the check LED VI scale does not work on this device.

  You must allow an order any to be able to stop your curls.  A simple global variable would work well here.

• Not end timed loop

  In the attached VI, I put the loop timed to end once the delay 1 reaches zero. However the timed loop continues to run and stop only if I have OR both 1 and 2 delay delay. (Tried with different schedules for late 2 which are less lag 1, equal to 1 delay and more delay 1 - no chance unless it is also linked to stop)

  What is the reason for this? (The VI is in LV2012)

  And it is protected by word that prevents us from looking into it.

  Is this your VI or did you also?

  Subvi properties seem to show that it is not reentrant.  Otherwise it can only run one instance at a time.  And if happens to store data to leave once it is called to another in the uninitialized shift, running an instance registers is probably interfering with the execution of the other instance.

• Structure of the event in timed loop

  Quick question on the structures of timed loops\event

  What is a good or a bad idea to use structures of event call loops - as opposed to while loops. ?  I guess I like the idea of call loops - because you can prioritize them - so if there are some important things you need priority of 100% in the background - but for the user interface, you can configure it to run slower\or run to a different priority level.

  I just wanted to check it is not a reason why I shouldn't do that - since all the examples don't do that.

  JP

  I don't think it's a good idea. Your timed loop can stop waiting for an event. There is no advantage of placing the structure of the event in a timed loop. It is possible to assign priorities to other objects outside of the call loops. For example, you can the priorities given to subVIs. I'm reasonably sure that the structure of the event can work at other priorities if you do not the activities of the user interface. Maybe someone of NOR can confirm this.

  But the goal of a timed loop is to have a deterministic periodic job. The structure of the event must be used for asynchronous events. The two disagree with them if they are in the same spot.

• timed loop

  In the timed loop, the entry node was a... of entry... that called "Source name" and says that I can specify the name of the source of synchronization.  What this means and how can I do?  How is it when I put a constant with the same name as the name of the default Source (create > constant > "1 kHz") the loop runs only x times then stops on its own.  Yet when I leave the value by default as is the loop runs until I hit the stop button?

  Hi Clint,.

  Yes, the moment Source.vi create will serve in the same vi. There is actually no difference between the vi and the options on the node of the loop. However the calendar source.vi creation will be used if you want to programmatically select the synchronization source.

  You will find information on the configuration of the source of synchronization in the detailed help, a link to which lie at the bottom of the window context help:

  "Double-click the node entry or with the right button of the structure and select Configure the timed loop to display the Configure the timed loop dialog box, where you can configure the timed loop. The values you enter in the dialog box Configure the timed loop appear next to the input on the entry node terminals. »

  Thank you

• Machine condition with timed loop?

  Hello world

  Is it possible to have a state machine with timed loop? i.e. on the last State, wait us here until the end of the period to return to the initial state again.

  Thank you

  crazycompgeek wrote:

  Hello world

  Is it possible to have a state machine with timed loop? i.e. on the last State, wait us here until the end of the period to return to the initial state again.

  Thank you

  Yes.  However, when the loop is running, there is no way to stop the program or do any other action.  But if this is what you want, yes it is possible.

• Sequence structure flat inside the timed loop and execution order

  I have some problems trying to implement a flat sequence structure when you use a loop timed on a target of cRio VI

  I tried with or without the while loop around the structure of sequence flat, and I also tried to replace the 'Non-deterministic loop' with a timed loop

  The problem is that the program seems to run only once, then get stuck somewhere

  I am writing a program that performs the following operations as soon as possible:
  1. read the Pos_MC of entry on the FPGA
  2 send the value of Pos_MC to the VI target (on cRio CPU)
  3. calculate a value of output based on Pos_MC with a PID block ("exit PID')
  4. send 'PID output' to the FPGA
  5 write "PID output" analog output "MOOG".

  In addition, I want the program to return the measured value "Pos_MC" to a host VI for the recording of data

  So that the output of PID is calculated and sent to the FPGA as quickly as possible, I placed a flat sequence structure to ensure that it happens before you send the output to the nondeterministic loop for recording data

  Also, I want the digital input 'Stop' to be able to stop the loop deterministic (the timed loop)

  I read much more entries than that and the help of several PID and exit, but I rewrote the code for a single entry and exit to make it easier to illustrate

  Screenshot of the code is shown in 'target code.png' and 'fpga code.png.

  The VI themselves are attached in the next post (cannot attach files of more than 3)

  Question 1:
  Any advice on how to get this race? Thank you!

  Question 2:
  Is also my correct understanding in that, using this structure, each 0.9ms (fpga loop time) comes the following:
  1. the input ("Pos_MOOG") is read on the fpga
  2. the production of PID is calculated on the cRio with some delay to computation (for example 0.1ms)
  3. the output of PID is then written for analog output "MOOG" in all about 0, 1 - 0.2ms
  4. the FPGA program then waits until 0.9ms spent and repeat the process

  As opposed to the next pass whenever performing a loop is started on the FPGA:

  1. the FPGA reads the input and written on the output (the output of the execution of the previous loop PID)

  2. then the entry is sent the cRio, PID output is calculated and sent to the FPGA

  3. the new release of PID is maintained until the next time through the loop

  Thank you!

  PHG wrote:

  Thanks for the input guys, any advice as to how I could get the feature in scenario 1?

  I still say that the best route is just putting all the logic of the control in the FPGA.

  Other alternatives include 1) the use of DMA FIFO sedn data back or 2) use interruptions so that the FPGA code can not read the output level until the RT.

  DMA FIFOs are usually very limited, and I would not use them in this situation since I belive said it this code to do for the many outputs.

• Is there a way to immediately interrupt a timed loop

  Writing a program that, when completed, im could run for a very long time. But I need a timed loop to run every 60 seconds. Option two, I came with are the following

  1 timed loop running every minute

  2 timed loop execution of every second, but treats the content of every minute.

  First way means that I can not stop the loop until the end of the period (more desirable than the 2nd option), the second option is based on the ability to determine when a minute until is based on a rate of iteration 1 Hz, but from what I read, the iteration count will eventually get its max value and simply hold its value the loop continues to run (that's why I lose my logic for the execution of content)

  I really hope, there is a way to make an immediate abandonment of a timed loop, but I'm not finding a way, lol

  

  If the registrant receives an error notification, it passes this error to the error node right over the untimed loop side.  In the contrary case the notifier expires and passes the node error when you want to iterate

• While why broken arrow will not appear for a timed loop

  Hi all

  I need a little clarification relative to normal while loop and timed looping in labview.

  In labview, if I keep a while loop on a block diagram, broken arrow will appear in the upper left corner of the window indicating the error. It displays error because I have not wired conditional terminal of the while loop.

  But same is not the case for a timed loop. Can someone tell me what is the reason behind this...

  If I release the conditional terminal of the timed while loop, it runs in infinfite time like a normal while loop. Then y labview behaves differently for these two types of loops in the scenario above.

  FYI... I'm using labview 2009.

  Waiting for response.

  Thank you

  Herald

  Ruben,

  the reason is quite simple: call loops are mostly real-time and FPGA targets. Since most of the applications on these targets work continuously (at least this is more often the task), it is possible to create a loop that does not end. So the timed loop by default assumes that there is no need of a stop button.

  The 'normal' while loop needs code for termination (conditional terminal) because normal applications on Windows/Linux/Mac are used to be fair...

  hope this helps,

  Norbert

• Impossible to click on the buttons for the timed loop.

  Hello!

  I have a loop that is timed with a pace set by the user. And when the loop is running, I can't push any button of my GUI to stop it...

  I have to wait until a mistake or I stop the race.

  I can't put the diagram is too big and I think I don't have the right, but you have ideas?

  Ask me for more details.

  Thank you

  bejard wrote: timed loop is just in a structure of the event and I put 10 ms or 100ms.

  The program runs correctly (with this loop delay of 10ms/100 ms) like in the beginning, but I can't push any button or even change the tabs during the loop.

  You shouldn't have long extensions inside the event.  Which is supposed to stop your timed loop?

  I think that you have the option "Lock the front until the end of the occurrence" lit.  It will not press anything, until the end of everything for this case (including the timed loop).

  According to my experience, using a loop timed in a Windows system is a complete waste and often adds more overhead and questions.  Instead, I really think you need to use a State Machine.  When the button is pressed, you tell your state machine to move to the State the code inside your timed loop tracks.  You can use the State with the structure of the event to time your loop.  If you can go behind your state of event to your processing loop structure.  Just set the timeout on the structure of the event at any rate of loop you really want to.

• run inside once timed loop

  I have a timed loop that monitors the equipment. Whenever there is an error I send a notification by e-mail. My problem is how to stop send e-mail whenever the time loop is executed. I tried placing email it inside a loop, but quickly realized that the whole of the loop itself is reiterted. Any help is much appreiciated.

  You can also consider using the first call? under the range of synchronization primitive.

• passing the value and to timed loop

  Hello everyone,

  I'm working on a VI that consists of a timed loop which takes values in a file every 6 ms and writes it to an output file. Inside this timed loop, there is also a MATLAB block that calculates a parameter based on the value. based on this parameter, that a marker is set to 0 or 1 (planned) to operate as a Boolean marker.

  The problem arises when the marker is set to 1. I need an additional structure any that waits five seconds (without stopping the timed loop iterations) and a 'stop' button is not pressed an additional string is placed in the output file. I wish for the marker to get back to 0 if you press the 'stop' button and not string to put in the file.

  The main problem seems to be the use of a structure outside the timed loop. I can't have a while loop or any structure that waits 5 seconds inside the timed loop. And if I let him out he does not have the value of the marker second structure during execution of the timed loop.

  + Any ideas on what the structure to be used during the 5 seconds Timeout? (I tried a while loop)
  + Use a local or global variable for the marker? (I tried briefly, but as a local variable, I couldn't choose a variable defined in the MATLAB block, and I don't understand global variables in LabVIEW)

  I enclose a simplified version of the VI as well as a sample input file in case it can help visualize.

  Thank you
  DAVA

  So far, there are a few problems with your solution, but first of all, I will try to help answer your original question.

  You are right that you can't have a structure inside the timed loop which waits five seconds without blocking execution of the timed for the same period. You are also right that you cannot simply communicate through cables to an external structure. If you exit a loop of wire in the other, which creates a dependency of data flow, which means that the data loop cannot run at all until another loop ends its execution entirely and send data.

  You have two options:

  • Don't actually use a wait function to determine if the 5 seconds elapsed. Use the Express VI of time elapsed (search the palette). He just guard track of how much time has passed since the last reset. It does not wait. If you are safe to use inside your loop timed in a case that is triggered when the marker value becomes 1. Also check the Boolean command in this case Structure to decide if you should output the data in the file.
  • Use an outer loop as in the example you posted, but use screws of the range of synchronization to send data between the parallel loop. Consider a queue.

  But overall, I don't think there is much chance of this work very well. No way, the Matlab Script node running fast enough to run at a time of 6ms. Also no way it works in a deterministic way at all. He needs to communicate with an external program, so its execution time is really unlimited.

• FPGA: Vs timed loop Timer?

  Hello

  I would like to create a FPGA loop that runs at a fixed rate. Whatever if I use a timed loop structure or a timer loop express VI into a regular while loop? Under what circumstances should I choose one over the other?

  I understand that the timer loop approach can cause the code in the loop run twice before calendar is established (but this isn't a problem for me here). Are there other differences in the two approaches?

  Thanks in advance.

  JKSH wrote:

  But my question was about the differences between the use of "multi-cycle" Timed loops and VI express loop timer.

  In a targeted FPGA VI, all call loops are single cycle timed loops (SCTL).  This means that all the code in a SCTL must run in a clock cycle, so there are a few types of nodes cannot be used in such a loop.  In a used while loop with a timer, you can use a wider range of features, but the loop will generally run much more slowly.

  These documents may be useful to learn how to use loops clocked on FPGA:

  Using loops of Cycle time unique to optimize the FPGA VIs

  Optimization of your screws of LabVIEW FPGA: running in parallel and Pipelining

• Edge counting and Source of Timing for timed loop on the request for Acquisition of data - not acquiring data on specified rising edge

  Operating system: Windows XP

  Hardware: PCI 6259

  Terminals used: PFI0 and PFI2

  Counters used: Ctr0 and Ctr1

  IM developing an application for the acquisition of data where timed loop synchronization source comes from my PFI2 (using the string A of an encoder).  IM basically trying to acquire data based on the number of ticks from my encoder.  For the synchronization source, I use counter 1 to capture the rising edge and have the loop time-acquisition of data.  At the same time, Im using the counter 0 to count the number of rising edges so I know exactly in what tick data was acquired.  PFI0 and PFI2 are connect to channel A of the encoder.

  Questions:

  Timed loop acquires data at each tick, because when I discover the data (text) file is missing count of my encoder value.  Is it because there is a limitation on the Windows operating system?  I used a noculars to measure the frequency at the maximum rotation of the channel encoder and 6,757 kHz.  All solutions?

  Also, is there anyway I can route the source channel internally an encoder to generate synchronization source instead of using another counter?  I have attached my VI.

  Hello

  All the samples that you acquire will be read by LabVIEW in a sequential manner. Figure 4-21 on the M-series on page 80 (4-34) shows that you will acquire all the samples you request all channels that you enjoy in sequentially.

• What is error-1418 on a timed loop?

  Someone at - he never had error - 1418 on the timed loop terminal error?  It runs only once and I'm trying to run it on a cRIO-9004.

  There is nothing in this range listed under the timed loop error codes.

  http://zone.NI.com/reference/en-XX/help/371361F-01/lverror/timed_loop_error_codes/

  As always, thank you

  Jim

  

  Hi Jim,.

  I think that's what you're looking for:

  Synchronization sources available for LabVIEW timed loop by platform

  Kristen H.