than 25 ns sets sampling rate...

Hello

I'm trying to test the sampling rate of chassis cRIO 9103...

I created a simple FPGA project, for sampling sign this clock frequency of the FPGA equal to 40 Mhz (on by default). I applied 1 Mhz square wave to pin MISO DIO6/SPI, place one of the slots on the frame... I put a tick 'loop timer' in ' ' loop for every moment of picking (totally 32 sampling point).

input signals a cycle = 1000 ns (1 MHz) and I m planning see samples every 25 ns (40 MHz) on the graphical waveform. But the chart shows me only 10 points for 1 cycle like taking samples of every 100 ns instead of 25ns. (FrontSamplingRateObservation.png)

What is to be? If so, how can I get faster sampling rate...

I joined .vi photos of the project...

You can consider that the only timed cycle lines and the pipeline of the operation.

Tags: NI Software

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