USRP RIO TDD RF Switch

Similar Questions

• Muliple USRP RIO 2943R, synchronization and phase-locking problem

  I use 8 USRP RIO 2943Rs transmission of signal and receving (4 for Tx) and 4 for Rx I'm using the "signal-based" method for synchronization of all devices. And I did it. I tested the system the result is very interesting:
  1. when I put the sampling rate of less than 40MS/s IQ, I can obversve very good phase locked Tx and Rx signals (I use a sine wave CW for tests), please refer to video joint (locked 40MSs)
  2. BUT, when I put the IQ more than 60 MS/s sampling rate, I'll lose phase lock. Please refer to unlocked 60MSs. My goal is to run the system at 120MS/s
  I have doubt as to if the problem comes from two sides:
  a. the sync methed isn't fair
  b. OR, should I increase the clock that operates the loop 'In Streaming radio engine' in the FPGA VI. as shown in the following image.

  

  I would like to ask experts in the forum to discuss the solution of this problem.
  More information about my system setting:

  

  
  

• Problem of generation of Sync trigger in several synchronization USRP RIO 2943R problem

  Generation problem shutter Sync in several synchronization USRP RIO 2943R problem.

  Previous SR you may already know I'm stacked in USRP RIO multiple synchronization problem, especially in the mode based on the signal. Now I can cut down, the problem is mainly due to the outbreak of sync signals generation.

  First of all, I read the article and the discussion in the following two links:
  http://forums.NI.com/T5/USRP-software-radio/how-to-synchronize-multiple-USRP-Rio-294x-devices/TD-p/3...
  http://zone.NI.com/reference/en-XX/help/373380D-01/usrphelp/synchronization/

  and I did my connection of the material according to the suggestions in the second link. My system schematic is shown in the following image:

  

  I checked OctColck and SMU 6674 T connections. They are all connected correctly and the cable are fine. I use the niUsrpRio200_XcvrSyncPps.lvbitx.
  According to the description of documents and discussion forum, the USRP RIO 1st in the list of devices are considered to be the USRP Master. Then, the FPGA to master USRP RIO released "trigger of sync" signal through the 'PPS Trigger Out' SMA port in RIO USRP box.
  Based on the my analysis of the system, the first impression I have is the USRP Master does not export the 'sync trigger' correctly. The host VI reports the error like this:

  

  I was trying to measure the "synchronization trigger" using oscilloscope, but I found that it is impossible, because the host VI can not yet run, so there is that no signal can be seen from port 'PPS Trigger OUT.
  So I think that if I can watch this signal "sync trigger" in home VI by importing this signal from FPGA to host VI. I did some changes on the FPGA VI as shown in the following image to watch this signal of façade of the host VI. but not so successful. the rx.start tragger relaxation and tx.start do not appear on the host vi read/write control function.

  

  

  
  

• USRP N210 connect through SWITCH GIGABIT

  Hello

  A quick question to make it easier to work.
  Now, I use 2 computers to the internet and work with the USRP.

  Is it possible to connect my computer AND usrp to a gigabit switch so I can use internet and at the same time the USRP?

  The subnet I receive is 10.67.49.1, so I give 10.67.49.2 my USRP.
  My computer is assigned a random ip address in the DHCP-here beach. 137, but I can't see the USRP (not in the cmd > arp - a, not in of usrp config util). Even when I change the IP of my computer to: 10.67.49.3 it does not work...

  But when I connect the usrp to my computer and use static IP address, it recognize...? Or is it just not possible...?

  USRP n210
  Windows 7

  Thanks in advance

  
  

• USRP RIO as BS and EU

  Is it possible to use USRP RIO for BS and EU side? Several USRP Siu can connect to NBS?

  Hi varugantigopal,

  It is certainly possible to use USRP RIOs for the EU and the BS and for several Siu to connect with NBS. Our MIMO Massive reference design, for example, uses up to 64 USRP RIOs the BS and 6 USRP RIOs to the equivalent of 12 Siu.

• USRP RIO 2953R firmware update

  Hello world

  We use NI USRP RIO 2953R with LabView 32bits. We are trying to run the example, the VI "niUSRP EX Rx Async.vi continues", but it returns an error in the GUI.

  Open Session.vi Rx niUSRPa runtime or configuration error.
  Code: 1440
  Details: RuntimeError: should FPGA number 0 x 6 compatibility, but got 0x9.0:
  The build FPGA is not compatible with the host code generation.
  As an administrator, run:

  "C:\Program Files (x86)\UHD\lib\uhd\utils\uhd_images_downloader.py.

  I guess I have to perform a firmware update to run the example VI, because he said that it indicates if the utility of Configuration NI USRP. Please also the attached photo. However we do not know what image file to download or burn. In contrast, we find also that the manual suggests not the firmware update for NI USRP 294 x or x 295 if you want to change the behavior of the FPGA?

  Do you know how I will deal with him?

  Rui

  Hello

  1. make sure that "Update Needed" message persists even after reboot of the device and and re-enumeration of the device by using the utility of Configuration of NOR-USRP.

  2. If the message persists, go to the tab 'Image Updater'.

  3 and select the device that you want to update the image on. Once you select the device that the path of the image will be automatically updated. If it does not go through this path of the image: "C:\Program Files (x 86) \National»

  4. write the image in the camera.

  5 restart the device and re - list and check that the "Update Needed" message no longer exists.

  Thank you.

• SISO TDD OFDM Streaming Video on NEITHER RIO or FlexRIO USRP

  Hello!

  How has the Full Duplex was assured in USRP RIO?

  In accordance with the document of this example, the simultaneous transmission of receiver chain is possible at the same frequency. If I take this right has component the interference of the transmitter Tx1 and RX1 was completely canceled for transposition Full Duplex.

  Or the FD is possible for an arrangement of the antenna?

  Thank you

  Understood that here Full Duplex doesn't mean full-duplex, we speak in reception and simultaneous transmission of documents i.e. contemporaries.  Here, it's a TDD system, where two data sources can be listened in conjunction, rising and falling, for example as in the No. loopback condition.  Simultaneous, albeit two multiplexes in time, flow: downlink uplink (base station user) (base station for the user).

• How to synchronize multiple devices (294 x) Rio usrp

  Hello

  I'm trying to receive 4 channels using two devices USRP-294xR (USRP RIO) to synchronously and run the example for the reception of several device program.   Often, I receive the error message "failed synchronization.  If I run the example several times in a row, this error message occurs more often than otherwise, but for all the times that he does not, I am able to collect data that seems like synchronous through the channels of reception.  So, in a way that works for me, but with the annoying feature that I need to run the program several times now until I am able to avoid the "Synchronization failed" error

  My installation includes an Octoclock connected to the Ref connections in and PPS in the two USRPs.  In the example, VI, I selected Ref in, but it is clear to me what choice should I use for relaxation.  Possible options are: 'Software', 'Immédiate', "Digital Edge", "Rx Start Trigger" and "Tx Start Trigger.  I had assumed my previous experience using these devices with the FPGA Ettus I would choose an option indicating that I tried to synchronize the external signal of PPS.  "External PPS" is not among the options of trigger, I'm confused as to how the synchronization.

  I saw the article below, but it's not not clear for me if I should be able to achieve my goal without making changes FPGA. It is possible to synchronize multiple devices using the program by default FPGA and example (i.e., for example RIO, not the host screw using the Ettus FPGA image)?  If so, any suggestions to help me avoid this error "synchronization failed"?

  http://zone.NI.com/reference/en-XX/help/373380D-01/usrphelp/synchronization/

  Thank you.

  Rob

  rkossler1 wrote:

  Since we did not have a 6674 t, I thought I might as well try to connect PPS from a RIO USRP to PPS on the two RIOs USRP.  I just used a BNC - T to "distribute" the relaxation.  It did not work - maybe for the same reason you mentioned on the PPS USRP out is not strong enough for the Octoclock by car.

  Yep, that's exactly it. The USRP RIO is not output enough power on the PPS TRIG OUT line to drive the lines of PPS TRIG IN two USRP RIOs, unfortunately

  rkossler1 wrote:

  How can I know which USRP RIO is the 'master '?  Do I need to designate in the software?  I chose arbitrarily use the device for which I have connected the PPS on the BNC - t 'RIO0', but I don't know how the SW knows what USRP I chose to connect the power cord to.

  The USRP captain's exit a PPS TRIG OUT in PPS TRIG IN sound. then all the USRPs you set this unit as the * first * device in the table of features of RIO for the façade of synchronization with a cross screw.

• The NI USRP-295xR RIO allows a front-end Ettus BasicRX IF-sampling? And what is the rate of the ADC to FPGA data?

  Hello!

  I'm in the quest to replace some aging PCI-5640R. I am currently using as a portable-Journal data solution, mounted in a Magma Expresscard to PCI box with a laptop. As a reference of the time, I use a Symmetricom XLi.

  The equipment is dependent on the sampling finished a set of samples once a trigger signal goes high and also receive antenna azimuth information using two lines PFI more. The signal is sampled at IF, 30 MHz, and the signal is less than 5 MHz bandwidth.

  Now, I started watching the Ettus X 301 with a GPS OCXO and MXI-express interface which should be the same as the USRP-295xR NI. It is available as device NI RIO with three different front ends, unfortunately, none of them work at 30 MHz.

  Q-1: Ettus has the front-end 'BasicRX', but it is only considered compatible with LabVIEW driver and not necessarily with the RIO. Is the front-end BasicRX usable with the USRP - 295XR RIO and MXI-interface with LabVIEW FPGA? Should I just avoid trying tune the nonexistent LO? As long as he gives me data, I can live with some error messages during the Setup...

  It's the best solution for me, but if it is absolutely impossible, I have a few questions:

  Q-2: information on the front end are really rare in the pages Web OR both Ettus, but the WBX is listed up to 50 MHz frequency, to have a filter of low pass of bandwidth of 40 MHz to I and Q. This should mean a total of 80 MHz of bandwidth with I and combined Q,-40 to 40 MHz. Why did the bandwidth to Web pages as OR listed being "40 MHz bandwidth in real time", if the low pass filter of the WBX is 40 MHz in I and Q? Not the band total bandwidth or 80 MHz?

  Q-3: assuming a bandwidth-40 to 40 MHz: could I put the WBX LO at 50 MHz, be tuned to the frequencies from 30 MHz to 20 MHz signal,-20 MHz and use a bandpass filter to the FPGA to extract the new signals and remove all other signals?

  Q 4: I tried to start a FPGA project in LabVIEW and add the x 301/294xR/295xR as a target. Data clock is locked to 120 MHz, which I guess means he will receive no data to 120MS/s IQ? The x 301 Ettus is listed as provide data of the ADC to the FPGA at a rate of 200 ms/s, could someone explain to me why, OR USRP RIO expects only database 120MS/s?

  Hi Idar,

  Yes, you should be able to put the basics on your X 310/USRP RIO and use LabVIEW FPGA to receive 120 MECH. / s of the DACs.  The example I posted is in fact not for the precompiled file bit.  The example I posted is for LabVIEW FPGA, which allows you to add the IP address for the FPGA.  There is a sample project that comes with LabVIEW FPGA which is the recommended starting point to build your FPGA application.  The sample project has all the configuration set up as well as broadcast continuously and pads/FIFOs in the FPGA and examples for synchronization.  There are comments in the code example that show where he must add your own blocks of property intellectual as a filter and decimater you mentioned.  The PDF I posted shows what changes you must make to this sample project using the Remora Basic/LF.

  I would like to know if I'm not explaining this clearly, or if you have any questions, I'd be happy to help you!

• LV 1.1, 14.5.1, 2950R USRP, DSP overflow using the example of Streaming Single-Device

  Hello.

  I use the SDR LabVIEW 1.1 and the USRP 14.5.1 with USRP-2950 device driver. Recently, I tried to use the interface of RX-host of the 'USRP RIO 40 MHz BW Single - Device Streaming PC' - example. Although the USRP device is connected to the PC via the MXIe card I get an error of overflow DSP (continuous mode). In my view must avoid an overflow of DSP for the chosen bandwidth and sample rate (examples in screenshot).

  If someone else gets this error or do I have to contact support OR? I already crushed the FPGA Image with the "NOR-SURP Configuration Utility.

  Thanks and greetings

  
  

• There is no help for the usrp blocks screens

  For power, where are the docs for help for the USRP & USRP related blocks (host side & lvfpga blocks)? Help is dimmed in the menus. If they came with the driver, they should be grouped in with something not obvious & has not installed. Where are they?

  BTW, I use NU-USRP 15.00.

  Thank you.

  apchar,

  Try to use context-sensitive help on the pilot of the USRP RIO screw Either click on the "?" in the upper right corner of the block diagram, or press Ctrl-H and hover over the screws of RIO USRP. You should see the additional help documentation.

• measure chain Gain in TDD system

  I want to measure the gain of the channel between pairs of RX - TX during each symbol using view USRP RIO and laboratory Communication Design Suite.

  Meathods suggested? Are there features of RSSI measurement?

  A known signal.

  Receive the signal and measure (n) ^ 2 + Q (n) ^ 2, given the elements of signal, which essentially corresponds to the signal strength.

• Rare use FPGA build without sample FPGA build

  Hello

  I hope I can formulate my question in the right way. I want to test a routine of FPGA and do not always want to compilate hole streaming project (e.g., construction with bus register etc.). Is it possible to only build a simple FPGA bitfile (simple while loop, some fifos, my code) and test on the device of the USRP RIO or what I need to use the basic FPGA in Streaming Xcvr as base build? This would be really shorten the compilation time to test the new code.

  I hope that my question is understandable.

  Concerning

  Etuel

  Yes, you can start from a blank VI FPGA and develop FPGA code similar to other LabVIEW FPGA targets. There are a few things to point out:

  • You will not be able to use the host of the project example screws if you do this. If you don't have the FPGA of the sample project code, the host screws will not good FPGA logic to connect with.
  
  
  • I recommend not to put any code in the domain of Data Clock. Data clock requires the USRP RIO IDLs configure this field of clock. To do this properly, you need the '' necessary '' of the FPGA block diagram section. It is easier just to avoid all this. To use the clocks faster than the clock of 40 MHz, derive a new clock, the clock of 40 MHz.

  Good luck!

• Automatic loading error on powerup

  Hello

  I have 2943R. In MAX, when I try to select "autoload on powerup" for the firmware, I get the error as in the attachment:

  There was a problem, save the settings for this device. Error code: BFFA86B3

  Is there a way to fix this?

  Thank you

  Ozan

  The USRP RIO always starts automatically at start/restart. The error you see is if you try to change its default value. What is the use case that you are looking to take in charge? Maybe that is already supported?

• Example of NEITHER RIO USRP LabView

  Hello world

  We begin to famaliarize oursevles with USRP AND 2953R. Is there an example project in LabView which is similar to the sample of streaming media project in LabView Commnuication Rx?

  Thank you very much!

  Rui Wang

  I found myself. 'S called it Simple USRP project LabView streaming.

  You may need 2014 LabView, the LabView FPGA module installed.