Waveform complex of FPGA (PXI-7852R) Lock-in Amp.

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  I would like to create a complex periodic wave (digital) with my PXI-7852R.

  After checking the article here on the generation of periodic waveform with cRIO and then for a few hours trying to get this software to work on my fpga (PXI-7852R) I'm not much closer to making it a reality.

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• FPGA (PXI-7852R) Square Wave DIO

  I need to improve the noise to the DIO square pulse pulse width. With my current code (attached .png) I see 25 ~ ns jitter on the front coming down from the impulse (I have the trigger on the rising) with my oscilliscope. This Jig is present even with only a single output square wave (i.e., I delete the other square wave generators).

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  25 ns is the period of your clock to 40 MHz, the jitter is unavoidable at this clock frequency. The DDS square wave algorithm produces a very precise frequency over time, but cannot control the speed at which it is called to update.

  If you set the clock of the loop to a greater frequency of derived clock, you shoot the Jig by the same factor. Right-click on a 40 MHz clock embedded in the project with the FPGA target and choose new clock derived from FPGA. You may need to experiment a bit to see how high you can set the clock frequency without introducing sync in compiling violations; new targets will allow higher clock rates generally. Set up your single cycle timed loop to use the derived clock and don't forget to update your average square configuration with the new clock frequency.

• Loops FPGA (PXI-7852R)

  I created two pieces of code that run as desired independently. It creates a sine wave, reads analog input waveform and concludes the relative phase. The other piece of code creates three waves with independent settings (freq, duty cycle, etc.). When I try to put them in the same vi only the first code runs. Square waves are not generated from the second code.

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• PXI-7852r

  Hello

  I currently have a PXI-7852r, and I try to get the data from the FPGA for post-processing of vi map.  I wrote a simple loop to retrieve the data from the fpga, but when I move it to the host vi I start getting time values.  For example, I say the card wait 50 usec between samples and it does but when I run the host vi my timing goes haywire.  I guess what I'm asking is how can I get the card data sampled at usec 50 to the post-processing step.

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  Depending on whether you want to raise or not your acquisition, on the side of the host of VI may need to be slightly modified, but the provided VI must be a good starting point.

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  I have to read the voltage level of a Lock-In-Amp and on the other to read the magnetic field of a Gaussmeter, simultaneously. After that, I should I establish a curve of respect of tension on the ground. Please give me some tips to write a good program with LabView to the stated purpose.

  Records,

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  Hello MrHappyAsthma,

  I'm looking at your code, and I see that you have two sessions of acquisition while the example has an acquisition and sessions of a generation. This could be the reason for the error.

  The digital data control are done right click on the front panel, then go on modern > I/O > digital data.

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• FPGA device configuration, package and speed grade.

  Hello.

  Where can I find the news of grade package and the speed of the FPGA inside of the PXI-7842R? I ask because I want to build a project XPS in the Xilinx XPS and program needs this info.

  I followed the example in the "how to use designs based on Xilinx Microblaze with NI LabVIEW FPGA 2009 and the R-series modules". There, he gives the info for the specific FPGA (PXI-7852R and PXI-7953R) they use. It's a Virtex5, ff676, xc5vlx50, level-1 speed, but the authors do not mention where one can find this info.

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  I would like to look at the FPGA PXI cards nor 7854r.  I rate of 750 kHz, 1 MHz AO.  According to the involved treatment, you might expect between 200 and 750 kHz closed control loop.  If the treatment is very intense, it's probably something less than 200 kHz.

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• Deploy with fpga after change of chassis.

  Hello

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  For development, I used a chassis PXI-1000 b.

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  The only way I deploy the project is to remove the FPGA of the nivssdf and remove the NI PXI-7852R of the chassis.

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  Matteo

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• FPGA - count inside a statement box

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• The initialization of the lut for FPGA

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  This must have something to do with the complexity of the LUT VI initialization.  As a work around, I simply wrote the data in a file that I then read for the initialization of LUT.  I have attached the screws again.

  The lack of reactivity is a problem, but also the absence of any indication of an error.