Xilinx FFT IP 7.1 (equivalent of 4-wire Handshaking)

Hi all

I'm trying to figure out how to get the IP of 7.1 Xilinx FFT to handshake properly as the 4-wire LabVIEW FPGA FFT Express VI. I need the use of Xilinx FFT because of the constraint of maximum length 8192 on vi express.

The common 4-wire for the handshake are:

ENTRY: entry valid

ENTRY: ready for the output

EXIT: exit valid

RELEASED: ready for the entrance

The Xilinx includes a few pins that are similar such as

OUTPUT: valid data

RELEASED: ready for data

OUTPUT: fact/edoné

ENTRY: Activate the clock?

Any ideas on the pins, I can use as INPUTS: input valid and ready for printing?

Thanks a bunch

Hi Jeffrey,.

I have attached an image I hope you find it useful.

Valid entry will match the activation (EC) clock pin

Output valid with valid data (dv) and

ready for the entrance with ready for data (rfd)

Let us know if you have any other questions.

Thank you

Tags: NI Software

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