Similar Questions

• The create a System Image will save the FPGA code and the RT code?

  I have some cRIO systems which were broadcast in our manufacturing plant for some time. A slight problem has been discovered in the programming and created a workaround solution, but a fix should be implemented. Currently, I have no way to test my new code without loading on the cRIO and it works on the tool while the product is running. If there is a problem and I need to do some debugging, the tool cannot be down for an extended period. I would write a vi that will save an image of the cRIO so I can reload the software that is currently running and prevent a situation of prolonged downtime.

  My question is, when I did in the past with a product that has different tests, calibration and the final client software RT, it seems that the code FPGA not be saved (not a big deal at the time since the new FPGA code was compatible with different deployments RT). The new FPGA code won't be compatible with the old RT software, so now I'm worried. I would like to just check on it until I have all the boss breathing down my neck. If the service will not save the bitfile FPGA, is there anything else I can do for the tool to return to the previous running state while I solved problems that may exist with the new code review? The original code was lost by my predecessor. Otherwise, I would use just that.

  Hi Jeremy,.

  You are right, because the create a System Image does not record the bitfile with the image of the RT. Using the configuration system API, you will need to deploy the RT image and then the bitfile FPGA compiled later. To ensure that you can return to the previous version of the software running on your RIOs, you could simply save the current image and bitfile before deploying the new image and bitfile.

  However, the best way to proceed is to use replication Deployment Utility (RAD of OR). I have provided the link to the tutorial on the wheel, where you can download the utility. This exe will make images of the any of your RT targets and will also include the bitfiles with them. You can also deploy these images to several targets at once. In particular, you can read about the Bitfile (s) configure for FPGA Deployment Flash; the bitfile will be deployed at the start when stored in flash memory.

  Replication and deployment (RAD) utility-

  http://www.NI.com/example/30986/en/

• LabVIEW FPGA code changes

  Hello

  I'm working on 802.11 application, I tried to change the FPGA code.

  I really need to compile all the code after changes? or just save the VI to observe the effects of the change.

  Yes, LabVIEW code must be compiled using the FPGA Toolbox after you make all the changes. I think the only exception is when you run mode simulated on your PC.

• Error of timing in my fpga code

  Hello everyone, I have attached an image with which basically indicates an error that I get when I compile my FPGA code. I am also attaching a photo of my code with it. I am a newbie in Labview FPGA and this code might not be effective way to achieve what I'm trying to accomplish. Basically what follows is the application.

  I have a sbrio 9642 and I'm six analog inputs and I would get the effective value of these six signals to be as accurate as possible. The entries are pure sinusoids with a frequency of 60 HZ.

  If anyone has questions about the code or demand, please post in this discussion. I will try to answer as soon as possible.

  Kind regards

  Kumar

  

  
  

• FPGA code will stop when the code RT

  I developed a FPGA code to manage a piece of hardware. It's the installer to read some default Panel control configuration values and then sit there constantly respond to signals input and output signal.  The bitfile FPGA is written in flash to load FPGA memory and starts almost immediately. So far, everything is good.

  Then I layered on the code of RT (cRIO-9075) system that opens a reference FPGA to the FPGA façade and allows me to follow a few indicators and change configuration settings and cause the configuration settings is changed be used by the FPGA.   So far, it seems to work too when I run the RT code interactively (eventually there will be an interface for a host system).

  The problem occurs when the code RT is ordered to stop. If you stop the RT code also, the judgment of the FPGA code and I will not stop the FPGA code. The RT code does not all calls to order the FPGA code to stop execution. When the RT code is stopped, the only thing she does in regards the link to the FPGA is to close the reference FPGA VI which was opened when the RT code was started.

  What should I do to cause the code FPGA to continue to operate as the RT code is started and stopped?

  I have to wait that I return to the office tomorrow to test this, but I think that this link has the answer to my problem.

  http://lavag.org/topic/16412-confusion-regarding-FPGA-Deployment/#entry100294

  It is said: "close FPGA VI reference. If you right click you have an option to close or by default close and reset. This means the VI FPGA is reset (read aborted in standard LV talking) when we close the reference. »

• FPGA code with the evolution of the modules

  I need to create FPGA code to a cRIO-9072 facing the development of the modules.

  My cRIO will have a number any NI 9203 (analog acquisition) and modules OR 9411 (acquisition digital) as inserted by the operator. When turning the power on, the system must identify two possible modules were inserted in each of the slots. Subsequently, he will then know what choices of code to call to acquire data from the individual modules.

  I found the article in the knowledge base for CRY that queries each module and again reports the type of module and I can use it to successfully detect modules, but what LabVIEW fails to allow me to do this is to compile my FPGA code that was designed to deal with possible modules. After compiling, I get the error: "IO found point FPGA project. You must add the I/O item in the Project Explorer window, or select a different element in the control of FPGA of IO or the constant"because the compiler requires the appropriate modules are configured in the LabVIEW project. Unfortunately, this would require two different modules to be configured for each slot at the same time as there are sections of code for the 9203 modules and sections for 9411 modules for all eight locations coexist in a vi.

  Anyone have any ideas on how to get LabVIEW to compile my FPGA code somehow?

  Many thanks in advance,

  With the current draft of LabVIEW FPGA, you cannot compile a LabVIEW FPGA VI which manages several configurations of C Series modules.

  For your application, you must create a target of your project for each of the possible configurations of module and build the corresponding FPGA VI. Then, compile each of the screws to create the necessary for each configuration FPGA bitstream. Then in your host VI, you can detect what the current configuration of the module and download the binary stream appropriate for the FPGA. Another issue to consider is that the reference to the FPGA VI/bitstream returned by the open FPGA VI reference function will be unique to each bitstream/module configuration. So in your host VI, you'll need treat each configuration of the module with a separate set of code by contacting the FPGA.

  If you consider only two different modules and an eight slot chassis, there are 9 modules possible combinations. The condition would be to the end user to place all modules of the same type together, either from the left or the right side of the chassis.

• FPGA code slows down suddenly

  I have the following code in the FPGA (didn't integrate the png because it is too big. You will have to click on the attachment below) and I noticed a bottleneck in the FIFO, when both running on the FPGA and jusing simulating values in the Dev Enviroment. Here are the values of control

  Sampling frequency - 1 ms

  Btwn samples - 1000 ms delay

  NB of static samples - 10

  I know that my conversion fxp is lousy right now and I will correct this, but I know that's not the issue. The question is in my FIFO because when I disable it everything works correctly. See the following questions which I will describe here is what I notice when I do not disable the part of the diagram:

  Running in the Dev Environment:

  Code works very well... for a while. If I look at the indicator loop counter it goes fast (about 1ms as programmed to do) of 0 to 9, then breaks for 1000 ms wait and then goes again. After about 20 all iterations of the loop, the for loop suddenly slows down way. I can see this because if I look at the counter of the loop, it starts to increment once every 5 seconds. I thought, well maybe the FIFO DMA reaches its limit, but is it not fixed? Old data should not only be overwritten? Is not delay because the delay indicator will never true so I have no idea whats going on.

  Running on FPGA:

  Never the time to fast as iteration above. From the outset, will slow down. I noticed this, because my side of RT, I have a dedicated loop to only read items in FIFO (see below). I put it to the top to read 340 items both (34 samples of table x 10 element). It takes forever for the FIFO reach 340 items (it should take only 10 ms). Because I have 1000 ms pause between entering the data there is no reason that my buffer should be overflowing.

  Suggestions? Sorry, I cannot post my RT code, but may be able to view the FPGA code if it is really necessary.

  Found the problem. The RTD I use by default in mode 'accuracy '. These RTD also do not have simultaneous sampling (NI 9217). In fine mode, the conversion time is set to 200 Ms. which explains why when I bench marked it took 800 ms to run one to the loop iteration (200 ms/Channel * 4 channels).

  To fix this, go to your project, click with the right button on any given RTD, choose Properties, change the conversion time of 2.5 ms.

• CRIO/FPGA code to run locally

  So I'm currently write code that will run on a cRIO (the processor in real-time and FPGA).  Is there a way that I can run on my computer without be hung to the material?  I do not have easy access to the material and would really like to test the behavior of my code.

  Thank you.

  Hello

  You can create a cRIO in your LV project without having the hardware, you can compile the FPGA code and run in simulation mode too, but you cannot run the code of RT.

  Christian

• Strange problem with my FPGA Code

  Hello

  I am running the following program, but I am facing a strange problem:
  -I can read all analog and digital input and write on the outputs analog (I measure the tension that I write on the map of the AO)

  - But the valves I have connected to the analog output, flashes a red light (which, according to the data, sheet means the electrical signal I send to them via the module AO is incorrect)

  -However, if I delete the ms and RMS block and do not make any average samples, but let all even (still two loops and two of the nodes separated from FPGA to e/s), the valves are operational and flash not a red light.

  I have a cRIO with four modules:
  -1. The (Mod1) AO cards
  -2. Map of HAVE it (2)
  -3. DI/O card (Mod 3)
  -4. Map to HAVE secondary (Mod4)

  I currently have two loops on the fpga all-in:
  -' Hand Loop (ML)': reads and writes I/O cards 1-3, with an expectation to 300us
  -'Top pressure sensors Loop (PACKAGE)' reads two HAVE the fourth module (Mod4), with no waiting

  These two loops are indicated in "fpga - part 1.png" and "fpga - part 2.png".

  The settings for the ms and RMS measures VI, as well as the façade are indicated in "fpga - part 3.png".

  The second loop uses 12002 ticks to run, the first loop use 160 ticks to run

  Previously, I had a similar problem which was fixed by setting the initial values indicated on the front cover for the analog output to the valves.

  Currently, I have not any target VI race and I'm only using fpga VI

  Any suggestions? Thank you!

  
  

• error after update 8.5.0 FPGA code generation 8.5.1

  
  
  

• Tests of changes in the fpga without reloading code

  I understand that after a fpga code is changed, it must be recharged in the fpga.  Is there a way to test the code fpga on PC without reloading the file bit in the fpga every time?  Thank you!

  Yes - with the right button on the FPGA target in the project and choose "run VI on...» "You can always run in simulated simulation with IO. Some devices take care of simulation with real IO so.  Of course it won't work not anywhere near the actual speed, but you can use the standard LabVIEW tools such as probes, highlighting the execution and debugging breakpoints.

• Why do I receive errors of internal software: Terminal Index out of Bounds. Code error-61350, when compiling my FPGA VI for a cRIO-9118 using NI 9223?

  I get the error (in a popup window) when my VI FPGA code in chassis 9118 OR NI 9223 module compiled help.  This error occurs when compiling the process (generating intermediate files, scene 7 of 7). How to solve this error?

  Thank you

  additional information:

  Original error message:
  -------------------------

  Errors:

  Software (s) internal error: Terminal Index out of Bounds.

  :-61350 error code

  Details:

  A terminal with this index does not exist on this block diagram node.
  NiFpgaHandleCallbackError.vi

  «"" "String of full appeal:»»"»
  NiFpgaHandleCallbackError.vi
  niFpgaNodeInformation.lvclass:Get Const Variant.vi
  DfirModGen.lvclass:GetConstant.vi
  niLvFpgaMungerBrainwashIONodeCommon_Dfir.vi
  niLvFpgaMungerBrainwashSingleIOGrowableMethod_DFIR.vi
  nirviEIOMethodImplementation_SpecifyDFIR.vi
  nirviEIOMethodImplementation_SpecifyDFIR.vi.ProxyCaller

  

  Hi tesa,.

  This is a bug that has been fixed in LabVIEW 2012 SP1. The number of CAR created for this bug is 332811 and as you can see in this link, it is already in the list of bug fixes.

  Carmen C.

• Integration of Code FPGA on the rest of the project.

  Hello, thank you for helping me.

  I recently started on the MyRIO, NOR I have the following code to handle a ultrasonic rangefinder:

  

  However, when I try to compile I get the message:

  

  Apparently many of the most common features of Labview can not be used on a FPGA target. However, the code for the Rangefinder is a small part of a larger project in which I have to use such functions, so my main concern is the weather, I'll be able to integrate this code with 'normal' labview FPGA code on the myRIO, if possible, how?

  I would create as for example a 'top' VI which has its own code (showing the waveform graph after the realization of certain mathematical operations on the will appear given by the VI as well as some other stuff).

  Thanks again for helping me.

  Here's the thing with FPGA: you configure real equipment.  Everything must be fixed to the size.  So if you don't have to use an array, you must configure it to be a fixed size (right click in the control to set the size, use the table to initialize or LOOPS containing a fixed number of cycles, and autoindexing).

  As GerdW said, FPGA is not a GUI.  So, you will want to use a DMA FIFO to send your data to waveform until the RT.  You create in the project.

  For some really good information, I recommend that you see the cRIO Developer's Guide.  The myRIO is the exact same platform as a cRIO except that you cannot use the C Series modules.

• Run code on the host target RT and FPGA

  Hi all

  I'm sorry if I ask a question to repeat. I searched for this a bit and couldn't find a solution.

  I'm trying to run a single VI (be it on RT compactRIO or on the connected host PC) and enforce the code on the host PC and target the FPGA code RT. I currently code that runs on the host PC computer that opens the FPGA reference and executes code FPGA, but I don't know how to do this with a VI on the target of RT. Any advice/help would be great. Thank you!

  Brandon

  You are not far from your goal. But you need to at least

  1. Update FPGA code (Bitfile) containing your code to run on the FPGA.
  2. An executable compiled for your goal of RT, which is set to autostart.
     You can use the code from my first post as a starting point. Compile, deploy and set it to autostart on your target of RT.
  3. An executable compiled for the host machine. that your user will begin.
     You can use the code in my first post, maybe load IP address, Port etc. of the Ini file settings.

  If you double-click on the exe file on your host computer it will open an application reference to your target computer of RT and call the VI on the target machine. This is how you run code on your RT. From this RT code you can download and run the FPGA (bitfile) to your FPGA code or control which is already running the FPGA by controlling a state machine code. Load more screws to your memory of RT targets and call them from your host to add more functionality if you need to.

• Optimization of DMA in the Code in time real (cRIO FPGA-> RT)

  Howdy,

  I am acquiring data from a microphone using the NI9234 module.  I wrote my RT and FPGA code.  I am communication of data between the FPGA and RT layers using a DMA FIFO.  I noticed that the layer of RT has difficulty to empty the FIFO, since the FPGA layer runs at a much faster pace.  I would like some pointers or suggestions on stupid things I do in the layer of RT that are causing it to run more slowly than necessary.

  Currently, my RT code simply opens the FPGA reference in a loop, extracts data from the FIFO and writes to a file.  I know that if I want to plot the data or perform an FFT on it, I would in a loop of lower priority, for not to slow down the data streamed from the FIFO.  Are there accessories simple performance that I'm missing in my code?  Thank you.

  I enclose a copy my code FPGA and RT (screenshots and screw), so that you can watch.

  I would seriously consider redesigning completely the code and using this reference request model.

  http://zone.NI.com/DevZone/CDA/tut/p/ID/9196

  There are reference points that show how this model makes.  With the acquisition of waveform, there are a lot of optimization.  This referenace application addresses all these to give you the best performance.