Similar Questions

• NEITHER 9234: sampling rate: cRIO, FPGA

  For the NI 9234 module, before Panel block diagram of my my cRIO FPGA code is as below.

  The sampling rate (speed) is selectable between certain values as shown below.

  You have an idea how I can do the sample with a lower rate that is smaller than the option of character (1.652 ksps / s)?

  

  

  

  Hi Cashany,

  Take a look at this link. Page 16 describes the limitation that you run in. The main time base are divided essentially only toward down to some data because of the way the camera rates physically handles analog and digital filitering. So it's not really a way to divide the beyond that point.

• Accelerate FPGA code

  Hi all

  I have a pretty "urgent" problem here:

  I wrote a FPGA code, I tested for a loop of 1 kHz with success rate before an important week of laboratory. Now I discovered that I need to increase up to 5 kHz sampling, however, I notice that my FPGA code can run that fast.

  As I am not this experience in FPGA, can someone give an indication on how to speed up the code?

  Thanks to you all.

  
  

• Optimization of DMA in the Code in time real (cRIO FPGA-> RT)

  Howdy,

  I am acquiring data from a microphone using the NI9234 module.  I wrote my RT and FPGA code.  I am communication of data between the FPGA and RT layers using a DMA FIFO.  I noticed that the layer of RT has difficulty to empty the FIFO, since the FPGA layer runs at a much faster pace.  I would like some pointers or suggestions on stupid things I do in the layer of RT that are causing it to run more slowly than necessary.

  Currently, my RT code simply opens the FPGA reference in a loop, extracts data from the FIFO and writes to a file.  I know that if I want to plot the data or perform an FFT on it, I would in a loop of lower priority, for not to slow down the data streamed from the FIFO.  Are there accessories simple performance that I'm missing in my code?  Thank you.

  I enclose a copy my code FPGA and RT (screenshots and screw), so that you can watch.

  I would seriously consider redesigning completely the code and using this reference request model.

  http://zone.NI.com/DevZone/CDA/tut/p/ID/9196

  There are reference points that show how this model makes.  With the acquisition of waveform, there are a lot of optimization.  This referenace application addresses all these to give you the best performance.

• The create a System Image will save the FPGA code and the RT code?

  I have some cRIO systems which were broadcast in our manufacturing plant for some time. A slight problem has been discovered in the programming and created a workaround solution, but a fix should be implemented. Currently, I have no way to test my new code without loading on the cRIO and it works on the tool while the product is running. If there is a problem and I need to do some debugging, the tool cannot be down for an extended period. I would write a vi that will save an image of the cRIO so I can reload the software that is currently running and prevent a situation of prolonged downtime.

  My question is, when I did in the past with a product that has different tests, calibration and the final client software RT, it seems that the code FPGA not be saved (not a big deal at the time since the new FPGA code was compatible with different deployments RT). The new FPGA code won't be compatible with the old RT software, so now I'm worried. I would like to just check on it until I have all the boss breathing down my neck. If the service will not save the bitfile FPGA, is there anything else I can do for the tool to return to the previous running state while I solved problems that may exist with the new code review? The original code was lost by my predecessor. Otherwise, I would use just that.

  Hi Jeremy,.

  You are right, because the create a System Image does not record the bitfile with the image of the RT. Using the configuration system API, you will need to deploy the RT image and then the bitfile FPGA compiled later. To ensure that you can return to the previous version of the software running on your RIOs, you could simply save the current image and bitfile before deploying the new image and bitfile.

  However, the best way to proceed is to use replication Deployment Utility (RAD of OR). I have provided the link to the tutorial on the wheel, where you can download the utility. This exe will make images of the any of your RT targets and will also include the bitfiles with them. You can also deploy these images to several targets at once. In particular, you can read about the Bitfile (s) configure for FPGA Deployment Flash; the bitfile will be deployed at the start when stored in flash memory.

  Replication and deployment (RAD) utility-

  http://www.NI.com/example/30986/en/

• FPGA code will stop when the code RT

  I developed a FPGA code to manage a piece of hardware. It's the installer to read some default Panel control configuration values and then sit there constantly respond to signals input and output signal.  The bitfile FPGA is written in flash to load FPGA memory and starts almost immediately. So far, everything is good.

  Then I layered on the code of RT (cRIO-9075) system that opens a reference FPGA to the FPGA façade and allows me to follow a few indicators and change configuration settings and cause the configuration settings is changed be used by the FPGA.   So far, it seems to work too when I run the RT code interactively (eventually there will be an interface for a host system).

  The problem occurs when the code RT is ordered to stop. If you stop the RT code also, the judgment of the FPGA code and I will not stop the FPGA code. The RT code does not all calls to order the FPGA code to stop execution. When the RT code is stopped, the only thing she does in regards the link to the FPGA is to close the reference FPGA VI which was opened when the RT code was started.

  What should I do to cause the code FPGA to continue to operate as the RT code is started and stopped?

  I have to wait that I return to the office tomorrow to test this, but I think that this link has the answer to my problem.

  http://lavag.org/topic/16412-confusion-regarding-FPGA-Deployment/#entry100294

  It is said: "close FPGA VI reference. If you right click you have an option to close or by default close and reset. This means the VI FPGA is reset (read aborted in standard LV talking) when we close the reference. »

• LabVIEW FPGA code changes

  Hello

  I'm working on 802.11 application, I tried to change the FPGA code.

  I really need to compile all the code after changes? or just save the VI to observe the effects of the change.

  Yes, LabVIEW code must be compiled using the FPGA Toolbox after you make all the changes. I think the only exception is when you run mode simulated on your PC.

• FPGA code with the evolution of the modules

  I need to create FPGA code to a cRIO-9072 facing the development of the modules.

  My cRIO will have a number any NI 9203 (analog acquisition) and modules OR 9411 (acquisition digital) as inserted by the operator. When turning the power on, the system must identify two possible modules were inserted in each of the slots. Subsequently, he will then know what choices of code to call to acquire data from the individual modules.

  I found the article in the knowledge base for CRY that queries each module and again reports the type of module and I can use it to successfully detect modules, but what LabVIEW fails to allow me to do this is to compile my FPGA code that was designed to deal with possible modules. After compiling, I get the error: "IO found point FPGA project. You must add the I/O item in the Project Explorer window, or select a different element in the control of FPGA of IO or the constant"because the compiler requires the appropriate modules are configured in the LabVIEW project. Unfortunately, this would require two different modules to be configured for each slot at the same time as there are sections of code for the 9203 modules and sections for 9411 modules for all eight locations coexist in a vi.

  Anyone have any ideas on how to get LabVIEW to compile my FPGA code somehow?

  Many thanks in advance,

  With the current draft of LabVIEW FPGA, you cannot compile a LabVIEW FPGA VI which manages several configurations of C Series modules.

  For your application, you must create a target of your project for each of the possible configurations of module and build the corresponding FPGA VI. Then, compile each of the screws to create the necessary for each configuration FPGA bitstream. Then in your host VI, you can detect what the current configuration of the module and download the binary stream appropriate for the FPGA. Another issue to consider is that the reference to the FPGA VI/bitstream returned by the open FPGA VI reference function will be unique to each bitstream/module configuration. So in your host VI, you'll need treat each configuration of the module with a separate set of code by contacting the FPGA.

  If you consider only two different modules and an eight slot chassis, there are 9 modules possible combinations. The condition would be to the end user to place all modules of the same type together, either from the left or the right side of the chassis.

• FPGA code slows down suddenly

  I have the following code in the FPGA (didn't integrate the png because it is too big. You will have to click on the attachment below) and I noticed a bottleneck in the FIFO, when both running on the FPGA and jusing simulating values in the Dev Enviroment. Here are the values of control

  Sampling frequency - 1 ms

  Btwn samples - 1000 ms delay

  NB of static samples - 10

  I know that my conversion fxp is lousy right now and I will correct this, but I know that's not the issue. The question is in my FIFO because when I disable it everything works correctly. See the following questions which I will describe here is what I notice when I do not disable the part of the diagram:

  Running in the Dev Environment:

  Code works very well... for a while. If I look at the indicator loop counter it goes fast (about 1ms as programmed to do) of 0 to 9, then breaks for 1000 ms wait and then goes again. After about 20 all iterations of the loop, the for loop suddenly slows down way. I can see this because if I look at the counter of the loop, it starts to increment once every 5 seconds. I thought, well maybe the FIFO DMA reaches its limit, but is it not fixed? Old data should not only be overwritten? Is not delay because the delay indicator will never true so I have no idea whats going on.

  Running on FPGA:

  Never the time to fast as iteration above. From the outset, will slow down. I noticed this, because my side of RT, I have a dedicated loop to only read items in FIFO (see below). I put it to the top to read 340 items both (34 samples of table x 10 element). It takes forever for the FIFO reach 340 items (it should take only 10 ms). Because I have 1000 ms pause between entering the data there is no reason that my buffer should be overflowing.

  Suggestions? Sorry, I cannot post my RT code, but may be able to view the FPGA code if it is really necessary.

  Found the problem. The RTD I use by default in mode 'accuracy '. These RTD also do not have simultaneous sampling (NI 9217). In fine mode, the conversion time is set to 200 Ms. which explains why when I bench marked it took 800 ms to run one to the loop iteration (200 ms/Channel * 4 channels).

  To fix this, go to your project, click with the right button on any given RTD, choose Properties, change the conversion time of 2.5 ms.

• RepeaterDemo.mxml run locally

  I can't get some of the Flex 2.0 samples running locally. In the Explorer of Flex 2.0 samples ( http://flexapps.macromedia.com/flex2beta3/explorer/explorer.html) the RepeaterDemo.mxml works fine, but when I copy the code in my FlexBuilder IDE I run into two questions.
  
  First of all, it seems that the ArrayCollection collection needs an ArrayUtils.ToArray ()...
  Second, it cannot find the name element in the product xml file.
  
  What is the difference between the code example for the Explorer for Flex 2.0 samples and running in eclipse?
  
  Code example
  
  <? XML version = "1.0" encoding = "utf-8"? >
  
  "" < mx:Application xmlns:mx = ' http://www.adobe.com/2006/mxml ' backgroundAlpha = "0".
  creationComplete = "srv.send ()" >
  
  < mx:Script >
  
  Import mx.collections.ArrayCollection;
  
  [Bindable]
  public var catalog: collection ArrayCollection;
  
  < / mx:Script >
  
  
  "< mx:HTTPService id ="srv"url =". http://flexapps.macromedia.com/flex2beta3/explorer/assets/catalog.xml ' useProxy = "false '"
  result = "Catalog = new ArrayCollection (srv.lastResult.catalog.product)" / >
  
  < mx:Tile >
  < mx:Repeater id = "list" dataProvider = "{catalog}" >
  < mx:VBox >
  < mx:Label text="{list.currentItem.name}"/ >
  < / mx:VBox >
  < / mx:Repeater >
  < / mx:Tile >
  
  < / mx:Application >

  The following code seems to work. Even if I was not exactly getting the errors that you receive, I received errors. "My key change used result ="Catalog = srv.lastResult.catalog.product as ArrayCollection collection instead of the result ="catalog = new ArrayCollection (srv.lastResult.catalog.product)" / >

  
  backgroundAlpha http://www.adobe.com/2006/MXML"="0"creationComplete =" srv.send () ">"
  
  Import mx.collections.ArrayCollection;

  [Bindable]
  public var catalog: collection ArrayCollection = new ArrayCollection();
  

  useProxy http://flexapps.Macromedia.com/flex2beta3/Explorer/Assets/Catalog.xml"="false ".
  result = "catalog = srv.lastResult.catalog.product as ArrayCollection collection" / > "

  
  
  
  
  
  
  
  

• Error of timing in my fpga code

  Hello everyone, I have attached an image with which basically indicates an error that I get when I compile my FPGA code. I am also attaching a photo of my code with it. I am a newbie in Labview FPGA and this code might not be effective way to achieve what I'm trying to accomplish. Basically what follows is the application.

  I have a sbrio 9642 and I'm six analog inputs and I would get the effective value of these six signals to be as accurate as possible. The entries are pure sinusoids with a frequency of 60 HZ.

  If anyone has questions about the code or demand, please post in this discussion. I will try to answer as soon as possible.

  Kind regards

  Kumar

  

  
  

• 12.1 T2K Delta 3 patch (8919489) ERROR + fails [code = 1] Running adjcopy.cla

  During the upgrade of database 11.1.0.7 to 11.2.0.3 as spots of pre - req
  12.1 T2K Delta 3 patch (8919489) fails with the ERROR [code = 1] Running adjcopy.class
  
  Environment is cloned - R12.1.1 and migrated to OEL 4 5 OEL
  ====================================================
  
  Updating of the Oracle Applications if necessary Java files...
  
  * $JAVA_TOP/META-INF/JRIMETA. DAT backup...
  
  Copy JRIMETA. DAT de JRIMETA. DAT. BackedupByAdpatch...
  Copied from JRIMETA. DAT de JRIMETA. DAT. BackedupByAdpatch.
  
  * Successfully supported JRIMETA. DAT.
  
  Adjcopy.class running:
  adjava-mx512m - nojit oracle.apps.ad.jri.adjcopy @/d02/applmgr/DEV/apps/apps_st/appl/admin/DEV/out/apps.cmd
  
  AutoPatch error:
  ERROR [code = 1] Running adjcopy.class
  
  AutoPatch error:
  Archives of master update error
  
  An error occurred during update of Oracle Java Applications if necessary files.
  Continue as if it was successful [No.]:
  
  ============================================================
  
  Please help me in this problem.
  
  Published by: user11958935 on August 18, 2012 22:39

  AutoPatch error:
  ERROR [code = 1] Running adjcopy.class

  You will find all the details on the error in the log file?

  Please see this doc ( Patch 13706647 R12 application error. BPM a: ERROR [code = 1] adjcopy.class [1455555.1 ID] running).

  AutoPatch error:
  Archives of master update error

  Please see if help solutions contained in these documents.

  During patch received: error [Code = 1] Running Adjopy.Class [397480.1 ID]
  Interoperability Patch 9935935 fails with error: 'IO error or zip, trying to read the README_share.txt entry in the zip file /java <$COMN_TOP>' [1288064.1 ID]
  11i: "Running adjopy.class ERROR: cannot create the file of success" error ADPatch using [1465401.1 ID]

  If you still have the same problem, please log a SR.

  Thank you
  Hussein

• Tools/database / SQLPlus broke my ability to run local applications

  Jdev 11.1.1.2.0
  
  I worked on a few practical applications for a few weeks. I was able to run their local and deploy on a dev server and run them from there.
  
  Yesterday I was looking through the menu items to see what is there and I clicked on tools/database / SQLPlus.
  
  I chose my connection and my SQLPlus.exe.
  
  SQLPlus worked fine, but now when I run my application on the built-in WL server it is stuck at the spinning O and never moves. If I update the stuck o it shows my app with no data.
  
  I'm fairly certain I don't change anything else between the time where he worked and where he was arrested.
  
  None of the applications that work work when I run local.
  
  When I open my DB connections and a hit test all return successfully. All DB in JDev tools seem to be functional, the only problem is when I run them on the built-in server of WL.
  
  I don't get any errors in the console and I can not find all the logs that contain errors, but I'm new on this and I can't look at the correct logs.
  
  I entered in config for and removed at runtime from SQLPlus, but which did not help.
  
  Any ideas?
  
  Is there a log somewhere that can show what is happening?

  Hello

  He doesn't have a problem with the WLS / approx. could you try with localhost (instead of 127.0.0.1) and also, you could try a different browser (IE/FF, say), and probably also a browser in another machine on your network?

  Arun-

• I need a code to run a report a forms on 10G...

  Hello!! I m 6i to 10G migration and I can not run a report... can someone send me a code example to run a report on a form in 10G?
  
  Thank you!!
  
  Kind regards!

  IAM using Javabean in oracle 10 g tun report forms...

  First, create a block with a name control and add a bean with a name
  userid_bean. Click the bean field and change its width and its height
  so that u can not see when you run the form.

  Now use the code when you code to run the report below.

  Declare
  rep_url varchar2 (2000);

  Start

  rep_url: = ' / reports/rwservlet? report = filepath\rep1. RDF' |
  «& desformat=htmlcss&destype=cache&userid=sample/sample@oracle» | '& paramform = yes;

  -Write Log messages to the console of JInitiator forms. The following line must
  -be disabled before running this code in any production environment.

  set_custom_property ('control.userid_bean', 1, 'ADD_USERID',)
  get_application_property (username) | » /'||
  get_application_property (Password). » @'||
  get_application_property (connect_string));

  -writes the cookie

  set_custom_property('control.userid_bean',1,'WRITE_USERID_COOKIE','10g');
  Web.show_document (rep_url, '_blank');

  end;

• ERROR [code = 1] Running adjopy.class

  Salvation of DBA
  
  When do I apply patch 5903765 I got the following error.
  I checked the owner's permission and write permission, it seems that everything is fine and I manually run following script, I got the same error.
  
  adjava-mx512m - nojit oracle.apps.ad.jri.adjcopy @/s03/CLONE/clnappl/admin/CLN/out/apps.cmd
  
  Kindly help me to solve the problem.
  
  =============ERROR=============================
  
  Subject writing cancellation archive: Monday, March 16, 2009 14:22:33
  
  Cancellation writing archive/s03/CLONE/kiranpatches/5903765/backup/CLN/aqherptestdb/java
  
  Error: I/o or zip trying to read entry meta-inf/jdev - ext.xml in/s03/CLONE/clncomn/java zip file
  
  Error (s) occurred; exit with status 1
  
  
  Java AD Run command is completed.
  
  Copyright (c) 2002 Oracle Corporation
  Redwood Shores, California, USA
  
  Java AD
  
  Version 11.5.0
  
  NOTE: You can use this utility to custom development
  unless you have written permission of Oracle Corporation.
  
  AutoPatch error:
  ERROR [code = 1] Running adjopy.class
  
  
  AutoPatch error:
  Archives of master update error
  
  
  Best regards
  SG

  SG,

  See the following note:

  Note: 376096.1 - i/o or ZIP while attempt to read/write error meta-inf/jdev - ext.xml
  https://metalink2.Oracle.com/MetaLink/PLSQL/ml2_documents.showDocument?p_database_id=not&P_ID=376096.1

  Kind regards
  Hussein