data delays cDAQ-9184 HAVE AO

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• Cannot get DAQ Assistant in Labview to cDAQ 9184

  I am trying to build a system for the acquisition of data with one NOR cDAQ 9184. I installed the drivers for the system and I'm able to get to the DAQ system using NI Max (under my system - devices and Interfaces - devices on network) and all channels appear well, however, I tried to follow the procedure described in http://www.ni.com/white-paper/11703/en/#toc2 to integrate my system with LabView and I am unable to find the tab software under the unit to be able to write the RIO 3.5.1 on the appliance and cannot find the device to through the LabView project.

  Your real problem is error-50103.  This is a common mistake, and you can find the answers for it if you are looking for in the forums.

  The problem is that you can't have several tasks (or several assistants DAQ) try to access the same device at the same time.

  Make a DAQ assistant who has all defined channels you wish to purchase.

• cDAQ-9184 AI DO

  Community of hell,

  I'm working on a chassis OR cDAQ-9184-one module (NI 9474) and two modules of it HAVE (NI 9215).

  The task is to acquire analog measurement and generate a pulse train to trigger a Laser sensor. Please find attached my simple diagram.

  The challenge here is to know how to sync the and GOT them. As a newbie in this area, I get several questions as follows:

  1. for synchronization multifunction, I need route my output internal counter to the task of AI as a sample clock. In NI MAX I can find this source in the advanced calendar section. However, in Labview, this CtrxInternalOutput is not available in the DAQmx Timing.vi.  Do you have an idea what could be the problem?

  2. during the measurement, I got 6590 HAVE measures and 6699 laser that are triggered by the pulse train with a sampling frequency of 500 Hz. It seems that we do not get the same amount of HAVE and. What could be the problem?

  3. information on this synchronization, in my opinion, we must configure the same sampling rate, the same same sample clock and HAVE & acquisition start together. Am I wrong? The difference in the number of samples is possible due to IT & do not stop at the same time, when I press stop in Labview?

  Thanks for your help.

  -sparkle

  1. the "Advanced" are hidden by default.

  2. There are two issues:

  i. you must start the task I face the task of meter output while he is in time for the first edge of clock.

  II. to make sure that read you the same number of samples in the form of impulses generated, you must stop the task of output of the meter and make sure you read back all the samples that were in the FIFO of AI.

  3 see #2.

  Best regards

• Data delay FlexRio (generate i/o of delay)

  Hello

  I use SMU-7961R + module NI 6583. I want to implement a synchronous digital communication IPs and I need control the master data of the clock delay.

  To contact a master external IP address, I use the struc timed loop with a clock source the strobe line where I connect the singal clock. The result is satisfactory: each master clock climbing aboard, data are generated with a specific constant delay.

  I have to control the delay (in the loop of the single clock cycle). This delay does not exceed 1 master clock cycle.

  In this case, the best is to include the buffers in the i/o path to the longest path... How can I implement this in LV FPGA...

  Note: Master clock isn't contineous.

  Thank you.

  Kay.

  Hi Marjorie,.

  Unfortunately, the maximum number of cuts will limit the total range of 5ns max, however 5ns is a period of clock at that point, you should be able to delay your data in the SCTL in LV FPGA.

  With respect to the generation on the falling edge, you have two options.

  The first can be done in LV FPGA but it's a little hard to explain. To build on the falling edge, we would first put the module in double data rate mode. Then, it will generate over and fronts. In order not to change the samples on the front, on the rising output must match the value of dashboard falling from the previous iteration of clock.

  For example, suppose you wanted the following values in the output order: T, F, F, t. you have to give a value for the rising and falling each iteration of the SCTL edge.

  Iteration 1:

  Rising - F

  Fall - T

  Iteration 2:

  Rising t

  F down

  Iteration 3:

  Rising - F

  Fall - F

  Iteration 4:

  Rising - F

  Fall t

  The one caveat to this approach is that you could generate only at 150 MHz DDR max of 300 MB/s.

  Another approach would be to reverse the polarity of the strobe in the CLIP 6583. This would require a VHDL work but definitely would make the LV FPGA implementation somewhat easier. Reverse the strobe clock in VHDL would also allow the refresh rate of 200 MHz.

  I hope this helps!

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• FDMEE error data import: No. periods have been identified for the loading of the data in the table "AIF_EBS_GL_BALANCES_STG".

  Hi experts,

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  Importing data in the rule of loading, I have encountered an error in loading.

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  I found a post related to this error, but did not respond.

  I know I'm missing something, gurus please help me to overcome this error.

  ~ Thank you

  I managed to overcome this problem,

  This was caused due to an error in the map of the time.

  In the mapping of source, the name of period should be defined exactly as displayed in the EBS.

  for example: {EBS--> OCT - 14} FDMEE {mapping source--> OCT - 14}

  The names of the time must be identical.

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