Open FPGA reference fails to run

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• Open FPGA references change to no. target when compiled with executable in time real start

  Hello again you useful forum fans!  I have a problem that I hope someone can give me a hand with.

  I have a project that has a Windows component and a component of the target in real time, that are running on a hypervisor type NI PXI-8110 system.  Communication both sides between them using shared variables.

  On the real-time side, I have four FPGA targets who are reading and writing various analog and discrete inputs and outputs.  I several periods loops which opens a reference to one of the FPGA targets during the first call, then pass this reference in several subVIs that read and write to panels prior to the FPGA.  The loops the FPGA reference thus made available and reuse it in the next iteration through the shift registers.  Each FPGA target has only a single reference open to him.  One of the loops is using the FPGA reference directly and does not pass it in any subVIs.

  It all works very well in the development environment, I can read and control inputs and outputs FPGAS via the front panel of the application of the side Windows.  It also works very well if I start the game real time in the development environment, and run the code of windows as a stand-alone executable file.

  However, when I compile the code in real-time in an executable startup and deploy it to the target, it does not work.  I enabled debugging on the executable, and when I connect to it via the operation-> debug executable in the menu, I see an arrow broken at execution.  Further investigation shows that each of the four open screw reference FPGA is now empty, the text under them is "no target" and the thread for reference on their part to my first Subvi is broken.  I need your help to understand how to operate as it does in the development environment.

  I followed the instructions of these two knowledge base articles to compile and download the bitfiles FPGA on the FPGA target and execute on start or restart:

  http://digital.NI.com/public.nsf/allkb/39795847AC67296D862575FB0046944F

  http://digital.NI.com/public.nsf/allkb/BC513C2A0DC29C89862574BF0002B0B9?OpenDocument

  Open FPGA reference screw are configured for the FPGA to build specifications that I created for each target in the LabVIEW FPGA project.

  I called technical support, NO phone, and yet were able to determine this one out, so additional "brownie" points if you do!  I would offer you the same no detailed screenshot that I have (I can't give more detailed code out because its owner, unfortunately), but apparently the forum doesn't like my image file, as I can't seem to load.

  Please let me know if you have any ideas regarding what is happening!  I appreciate it.

  Jon,

  I'm always up for the challenge.  Have you tryied recompile the FPGA VI that accesses the RT VI?  I also suggest to try and open the bitfile instead of the FPGA VI.  You run in dynamic mode (this is not a suggestion, it's just a question)? There is no difference if you try to open the FPGA VI reference outside the while loop, then past the reference to use inside the while loop without shift registers, then close the reference to the FPGA VI outside the while loop?

  Let me know if these suggestions makes no difference.

• Open FPGA reference FPGA VI

  I'm learning the FPGA.  I have a few simple question.

  1. I tried to use the open FPGA VI reference configuration.  I selected the file bit on my PC, and I checked the run option VI FPGA.  Why I select the bit file on my PC?  The file bit is not supposed to be on my FPGA target?

  2. once I open FPGA VI reference, I fed to an invoke node, but it won't.  It is said that the sources and sinks have given different type, but he also says that they are both FPGA interface.  I'm a bit confused.

  Please see attached picture.

  jyang72211 wrote:

  1. I tried to use the open FPGA VI reference configuration.  I selected the file bit on my PC, and I checked the run option VI FPGA.  Why I select the bit file on my PC?  The file bit is not supposed to be on my FPGA target?

  Not quite sure what you're asking here.  A FPGA target has no local storage.  When you open the FPGA VI reference, LabVIEW support the bitfile on the FPGA.  The VI that calls open FPGA VI reference is one that opens the bitfile, the bitfile must be local to this VI (in this case, on your PC).

  jyang72211 wrote:

  2. once I open FPGA VI reference, I fed to an invoke node, but it won't.  It is said that the sources and sinks have given different type, but he also says that they are both FPGA interface.  I'm a bit confused.

  The FPGA reference on the Panel before you must match the configuration of the reference that you're passing to it.  Right-click on the front panel control and configure the FPGA reference to point to the same bitfile you open.  Better than that, bind the FPGA VI reference open to a Type definition and the place that the category definition on the Panel the Subvi front.  Note that if you do this, it works at the back of what you would expect.  Update of the baseline open FPGA VI changes the type definition; you never directly change the type definition.

• FPGA open file reference difference calling bitstream or VI?

  Is there a difference in the behavior of the open FPGA Reference when you set it to look the VI against the bitstream file?

  Everything on different behind the scenes?  He link to the same bitstream file when you point to the VI?

  Thanks for the idea.

  
  

• error-61141 open FPGA VI reference

  Hello

  Plug-in a cRIO9074. I ran a scan EN Mode application, on the target that fontionnait. Then, in another project, I wanted to run a colorful mode FPGA application. The open FPGA VI reference then returns the error-61141 and indicates "Scan Interface is running". You must set the controller in FPGA Interface mode to unlock the FPGA". In the project window, I checked that the chassis was in mode FPGA. Moreover, when creating a new project RT, the discovery of the modules will fail with warning "FPGA is busy." The connection to the target is, however, possible, but takes several minutes. Information can be important: the first application in scan Mode established TCP communication with the host PC. Can this connection will hinder communication with the target?

  Thank you in advance pour your answer.

  Julien J.

  Hello

  I'm not sure what's going on. What I recommend is to completely reformat the controller and see if this can help you. I hope that you use the latest version of the NI-RIO driver.

• error-63198: short system resources when opening several references of FPGA Vi

  I am trying to open 15 Vi FPGA refenreces using 'Open FPGA Vi Reference'. Each connects to a FPGA, PXI-7842R card.  After restarting the system in time real PXI, the program opens only 6 references when it runs the first time, with the rest (9) failed with error-63198 code: System to run out of resources. Log and try the operation again.

  If the program runs the 2nd time, only 5 gets opened and the rest errored out. 4 gets is open for the 3rd time. 2 gets is open at the 4th time... until 0 gets is open at all times.

  After that I restart the PXI chassis, he repeated from 6 references open again.

  Any idea on what the problem is?

  Thank you!

  -The Ray

  Hi, Nick.

  The problem has been resolved. I was setting the resouce for each FPGA in its properties as "rio://100.0.0.3/RIOx" to match what he showed at MAX I also use the same string as the name of the resource to open the vi in block-schema reference. and it is wrong on with-63198.  After that I changed to a "RIOx::INSTR" or "RIOx" for all cards FPGA, then it works. Don't understand why he needed in this way, but it works. You can report future improvements if you believe.

  FYI, I've attached a screen shot here.

  Anyway, thanks a lot for your help!

  Ray

• Error opening of FPGA reference

  I use the 8.6 and all the latest versions of the software on a device cRIO. In my code RT I opens a reference to a FPGA file and when I do with this error to expire:

  error code:-63192
  in Kyle.vi CRIO-CRIO Kyle.vi host
  Activities FPGA:

  Open FPGA interface reference. in Kyle.vi CRIO-CRIO Kyle.vi host

  There seems to be no explanation of this error on the Web site of NOR, and I need help to find out why the error might be involved.

  OK, so I made a stupid mistake. The project I'm working on that uses 3 crios simultaineously. To simplify things, all cRIOs run the same screw on them and if necessary, they detect what crio they are on the fly.

  Well, because all crios use the same file I had only opened the structure of files on the crio first in the project. The error occurred because I do not have the FPGA files in parts of the second and third crios FPGA in the project. Either they were removed or never added when I created a new project (created a new project to resolve a previous error). Thus, when the reference the the bitfile was attempted to be opened on the second and third crios, there is no FPGA files in the build, so he would give this error.

  Quite embarrassing.

• Good way to stop and run again a FPGA reference

  Hi guys!

  I have some problems when I try to stop, and then rerun an FPGA vi, I explain.

  I have two DMA FIFO to send data to the FPGA of the CPU and the CPU for the FPGA. When it receives data, the FPGA treats them and sends them to the CPU, and according to the result of the CPU does something. For example, it can be turn on LEDs or to rotate a motor continuous.

  But to do these actions, I have to use a "personality FPGA", i/o pins and LEDs appear to be managed by the FPGA core. So I have to close my reference vi FPGA in charge to receive data from the CPU, make my power on LED and then after raise again my FPGA VI once again, if I don't do LED blink or stay without effect rotation motor... But close and start again the FPGA VI creates problems when running, especially for the previous reading on the FIFO DMA awaiting... I tried to intercept errors on the FIFO to restart the FPGA VI with a good time but nothing... I am lost and I think Miss me something, concept, or something else.

  I can't share my code because I work for a company, but I would like to know if you have VI with this type of structure: a FPGA reference that must be stopped to allow interaction of material with the FPGA default personality then run again, all with good timing...

  I hope I'm clear, but if it is not the case, I can rephrase if necessary.

  Thank you very much for the help!

  Afghow.

  I do not understand why you need to change the bit file is loaded in the FPGA.  Why you cannot add code that handles the inputs/outputs to your FPGA processing?  Why do you still need to send data to the host (CPU)?  Just having the process FPGA data and change the output directly.

• A single reference FPGA, 2 parallel FIFO running, how close the reference?

  

  The FIFO are being made of a single FPGA reference. If you see on the right the most, I have 2 close to reference, when I press the stop button, it gives me the error dialog box. What is the proper way to close the two FIFO?

  That is right.  The reason is because they are both the same reference.

• Impossible to check the FPGA reference with "not a number/path/Refnum?

  How can I check if an FPGA interface refnum is valid?  It seems (LabVIEW 2009) that "Not a number/path/Refnum?" always returns true when connected to the output of open FPGA VI reference.  I write code that needs to be able to run without an FPGA for testing purposes, so I wrapped all calls to the FPGA in a case structure that I thought would run only if the FPGA reference is valid.  Turns out that they run ever, even when the FPGA reference is valid (probe shows it has a numerical value, and the FPGA VI is running).  I guess it's sort of similar to semaphore and appointment of references that have their own special function to verify the validity, but I do not see such a function for FPGA.  I have to cast to int and check if it is not equal to zero?

  
  

• FPGA reference questions between the station development and execution? 63195 error code

  I will do my best to describe the problem, I was see.  Note, I tried a few other messages that kind of touch on my problems, but they never seem to have a definitive solution.

  Background-

  I have 3 screws:

  VI 1) opens / runs the bitfile FPGA reference and stores the reference to a global file so that I can call the reference of other screws I need to do this as opposed to the opening of a new reference because I use the FPGA for digital communications and it adds about 100 ms to to open a new reference whenever I need to read/write in the target FPGA to host (100 ms are long in the) digital world!).  Some people use Shift Registers.  I finally called my whole army FPGA screws of TestStand to run a test automated, so it was easier to break up of my functions for open/close/read/write.

  VI 2) called the global reference of the file for FPGA, then going to a read/write node to change the settings of the target, then passes the reference out of the node back to the global reference of the file read/writable

  VI 3) calls close reference FPGA and the function is passed the global reference of the file.

  Question-

  I understand not why this method works fine when I run either of TestStand with station options defined for the development (not running) mode or when I open VI which calls these 3 screws individually in sequential order but IS NOT working when I try to run these screws individually (Run VI 1 - open-> write Ref to the global reference of the file-> Run VI 2 - read global file reference-> playback control function / writing-> error-63195) or when I have run in the same sequence TestStand but together with station for execution options.  Maybe I need to change the TestStand sequence to load all the modules at startup?

  Why the reference becomes lost when global failover between development and execution and why labview cannot drop keep the reference stored?  Is there a work around?

  Finally found a solution.  I do not understand why it is necessary during the reading of the FPGA and not what writing (in fact I do not understand why it worked at all) but I ended up changing the properties of the step in my TestStand sequence for the step calling my DTL_READ.vi to be properties-> Run Options-> Unload Option-> "Unload after executing the step.  That seemed to do the trick to get my test TestStand sequence to work in runtime.

  I still don't understand why this was not required when you run the same sequence in the design environment and why it is not when I call my DTL_WRITE.vi.

  The DTL_READ.vi and the DTL_WRITE.vi pass the parameter labveiw global.vi 'Reference FPGA VI"of a node in read/write.  I don't know if the root of the problem is in my host TestStand and LabView FPGA VI...

  Thanks for all suggestions from you guys!  I'm happy I work but I am still confused by the solution.

• LabVIEW 8.6.1 project causes the slow open VI reference

  I have a strange problem with 'Open VI Reference.vi'.

  Case 1.

  • Open a project in LabVIEW that contains "Main.vi".
  • Open 'Main.vi '.
  • Run "Main.vi".
  • Execution of "Open VI Reference.vi" take about 2, 000ms

  Case 2.

  • Open "Main.vi" - open LabVIEW No. project
  • Run "Main.vi".
  • Execution of "Open VI Reference.vi" take about 100ms

  I converted the project to 8.5 and the problem goes away. I have not all machines with 8.6.0 to test if there is a problem with 8.6.1 only.

  Has anyone else seen anything like this?

  
  

• Several loops of RT; A single FPGA reference

  I have three loops using the same reference FPGA.

  Loop 1 - reads most of the data in the FPGA for display on the HMI

  Loop 2 - using the information made available to the loop 1 as well as some additional data that is read from the FPGA to perform the functions required by the HMI controls and writes for the FPGA.

  Loop 3 - uses data from Loop1 as well as additional data read the FPGA to run commands fuctions and wrote security for the FPGA.

  My questions are:

  The FPGA Refence points to a single memory block where all three loops are looking at the same data?

  I need on While loops shift registers to keep data updated correctly?

  I need to run the three sons reference FPGA close While loops to close the reference correctly?

  Yes.  N ° N °

  I assume you mean wire reference FPGA entering a node that reads the FPGA reference you speak or write in the Panel control or indicator that is part of the VI running on FPGA.

• It is possible to pass arguments to a VI uses "Open VI reference.

  I am modifying pre-existing code. (I say this, because there are many other ways to work around this problem, but I'm stuck with what I have)

  I have a large project that is compiled into an EXE file.

  Within this project, it uses the 'Open VI reference' in VI that is bundled in the compiled exe file.

  All good, no?

  Well, here's the question:

  Is it possible to include arguments of open type of command line with a "reference VI"?

  Where I can say "Something.vi / Option: Foo".

  

  I tried many variants such as

  ' Something.vi-/ Option: Foo ".

  even tried variations such as

  "C:\MyLVProgram.exe\Something.vi Option:Foo".

  (Interestingly, quite there no error when you do "C:\MyLVProgram.exe\Something.vi" when executing the VI reference opened.)

  This exe is deployed in a system that has only installed the runtime.

  My current environment is LV 8.6.1. (I know it's old)

  It seems that the antiderivative of LabVIEW recognizes only the paths, and in all other cases, I get an error

  Error 1026 to invoke the node in Something.vi-> MakeSomething.vi

  Possible reasons:

  LabVIEW: VI Reference is not valid.

  Any ideas?

  You can only send command line arguments to an executable with the system Exec.  If you want to pass data in VI, then use the asynchronous call with run.

• Open VI reference Cant find control

  Unless...

  From the beginning, I'm under LV2009. I open a reference to a global functional VI running on a remote computer to get the value that is in its "front panel indicator. I have two problems. The first is that when I use a string containing the name of VI, he will not find the VI. When I use the full path to the VI, the reference open VI works fine. Boring, but doable, because I have only about six FG read and they are all saved in the same folder.

  Second problem and the real reason for the post: I can get all the values of control as a variants without problem using Ctrl Val. Get all the method. But when I try to name a control in the method (Ctrl Val. (Get), I get an error indicating that the control cannot be found.

  SO, I used nodes property to get the text of the label and checked to see if everything was equal to the name of the command, I'm reading. It came negative. So I created a list of the labels out of the label. Property of text and node is the name I just checked for. So I copy and paste this back into the constant that is connected to the entry of the name of the control on the Val Ctrl. download Invoke node and no mistake. What the? So I delete the text I pasted in the constant and fix it and it still works very well.

  I checked and rechecked enough to know that I was not typing the name in wrong, but now it works fine. I can close the VI and reopen it, works very well. Type the name again. Still works fine. Any thoughts?

  DeskPilot wrote:

  Unless...

  From the beginning, I'm under LV2009. I open a reference to a global functional VI running on a remote computer to get the value that is in its "front panel indicator. I have two problems. The first is that when I use a string containing the name of VI, he will not find the VI. When I use the full path to the VI, the reference open VI works fine. Boring, but doable, because I have only about six FG read and they are all saved in the same folder.

  Second problem and the real reason for the post: I can get all the values of control as a variants without problem using Ctrl Val. Get all the method. But when I try to name a control in the method (Ctrl Val. (Get), I get an error indicating that the control cannot be found.

  SO, I used nodes property to get the text of the label and checked to see if everything was equal to the name of the command, I'm reading. It came negative. So I created a list of the labels out of the label. Property of text and node is the name I just checked for. So I copy and paste this back into the constant that is connected to the entry of the name of the control on Ctrl Val called node and no mistake. What the? So I delete the text I pasted in the constant and fix it and it still works very well.

  I checked and rechecked enough to know that I was not typing the name in wrong, but now it works fine. I can close the VI and reopen it, works very well. Type the name again. Still works fine. Any thoughts?

  An area located to the right of your constant original fits this description of the problem.

  May be useful...

  If you know the data type of the data that you read using the prpererty val node, you can use the node "to THE more specific" to set up your to the appropriate type. After that your val will not be a Variant, and you can use the standard LV operators to work with the data.

  Ben