Several loops of RT; A single FPGA reference

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• Open FPGA references change to no. target when compiled with executable in time real start

  Hello again you useful forum fans!  I have a problem that I hope someone can give me a hand with.

  I have a project that has a Windows component and a component of the target in real time, that are running on a hypervisor type NI PXI-8110 system.  Communication both sides between them using shared variables.

  On the real-time side, I have four FPGA targets who are reading and writing various analog and discrete inputs and outputs.  I several periods loops which opens a reference to one of the FPGA targets during the first call, then pass this reference in several subVIs that read and write to panels prior to the FPGA.  The loops the FPGA reference thus made available and reuse it in the next iteration through the shift registers.  Each FPGA target has only a single reference open to him.  One of the loops is using the FPGA reference directly and does not pass it in any subVIs.

  It all works very well in the development environment, I can read and control inputs and outputs FPGAS via the front panel of the application of the side Windows.  It also works very well if I start the game real time in the development environment, and run the code of windows as a stand-alone executable file.

  However, when I compile the code in real-time in an executable startup and deploy it to the target, it does not work.  I enabled debugging on the executable, and when I connect to it via the operation-> debug executable in the menu, I see an arrow broken at execution.  Further investigation shows that each of the four open screw reference FPGA is now empty, the text under them is "no target" and the thread for reference on their part to my first Subvi is broken.  I need your help to understand how to operate as it does in the development environment.

  I followed the instructions of these two knowledge base articles to compile and download the bitfiles FPGA on the FPGA target and execute on start or restart:

  http://digital.NI.com/public.nsf/allkb/39795847AC67296D862575FB0046944F

  http://digital.NI.com/public.nsf/allkb/BC513C2A0DC29C89862574BF0002B0B9?OpenDocument

  Open FPGA reference screw are configured for the FPGA to build specifications that I created for each target in the LabVIEW FPGA project.

  I called technical support, NO phone, and yet were able to determine this one out, so additional "brownie" points if you do!  I would offer you the same no detailed screenshot that I have (I can't give more detailed code out because its owner, unfortunately), but apparently the forum doesn't like my image file, as I can't seem to load.

  Please let me know if you have any ideas regarding what is happening!  I appreciate it.

  Jon,

  I'm always up for the challenge.  Have you tryied recompile the FPGA VI that accesses the RT VI?  I also suggest to try and open the bitfile instead of the FPGA VI.  You run in dynamic mode (this is not a suggestion, it's just a question)? There is no difference if you try to open the FPGA VI reference outside the while loop, then past the reference to use inside the while loop without shift registers, then close the reference to the FPGA VI outside the while loop?

  Let me know if these suggestions makes no difference.

• Cluster for the FPGA reference constraint

  I have a cluster of clusters.  One of the internal piles went 25-29 items, but I forgot to update several of my Subvi reflect.  I remember before when I did, I got a broken line not executable VI, but now the result is a constraint.  You can really force a cluster with multiple items to a cluster with fewer items?  My outdoor group consists of some FPGA with clusters of register references.

  Hi Adams,

  FPGA reference is the special data of type "FPGA dynamic reference", which includes a cluster of records, elements, and associated with the referenced FPGA personality FIFO dynamically. Dynamic data types do not follow the same rules of coercion expected of them a defined data type statically to follow. The dynamic nature of reference FPGA son allow wire any FPGA reference in the entry of an order of read/write, regardless of whether the control of read/write was created explicility for the FPGA reference. This makes it much more practical FPGA programming.

• Cannot use Select inside the loop For inside the SCTL (FPGA) - Bug? An alternative?

  When I put a Select statement inside a loop in a loop of Timed Cycle in LabVIEW FPGA, I get the following error when I try to compile:

  "An internal software error occurred. Please contact National Instruments technical support on ni.com/support with the following information:

  Error-61003 occurred at

  Possible reasons:

  LabVIEW FPGA: you cannot include this function in a loop For when the loop is within a single cycle timed loop. »

  I didn't know that whatever it is documented that says that this is not allowed; is this a bug or am I missing some documents?

  The code that causes this error looks like this, inside a SCTL (ignore Boolean wire wandering behind the loop for)

  

  I came up with the code below instead, which compiles into one Cycle timed loop, but it is a bit ugly. Does anyone have a better suggestion?

  

  This issue is currently followed under the CAR # 592391. Please keep an eye on our patches and new versions as usual!

• Table of clusters change an item in several loops

  Hello, sorry for my bad English.

  I have an array of clusters, clusters of other tables and controls.

  

  I want to access each control individually in the table, in several loops to avoid data loss. I know that I can refer to each control in the cluster and change its values, but he changes the values in the table too.

  

  Or I can access the cluster I want in the table, but I can't access each control individually.

  

  If I do something like this im going to given loose.

  

  So what can I do?. What is the most effective way to do it?

  Thanks in advance.

  Looks like you really need, it's a reference to value of data on the table.  Then, you use the Structure of elements in Place to access the array, the index of the item you want, and then ungroup by name to get the desired control.  Do the reverse to clean it up and save the data.

• combine several pl/sql in a single associative array

  Hello
  I use oracle 10g, can anyone suggest me how to combine several pl/sql in a single Bay.
  
  ex:
  

  TYPE t_array IS TABLE OF VARCHAR2 (100)
        INDEX BY BINARY_INTEGER;
  
     v_subnasp        pk_rules.t_array;
     v_product        pk_rules.t_array;
     v_order_type   pk_rules.t_array;
     v_combine       pk_rules.t_array;

  I want to combine the data in v_subnasp, v_product, v_order_type to v_combine

  DeepakDevarapalli wrote:
  Sorry, I think that my question is not clear. can I move data from 3 tables on a Bay. and what is the best way. I found a way using loops.

  If you declare an associative array type - loop is pretty much your only option. If you declare the nested table type, you can use operatots of type multiset:

  DECLARE
     TYPE t_array IS TABLE OF VARCHAR2(100);
     v_subnasp        t_array := t_array(1);
     v_product        t_array := t_array(2);
     v_order_type     t_array := t_array(3);
     v_combine        t_array;
  BEGIN
      v_combine := v_subnasp multiset union all v_product multiset union all v_order_type;
      for i in 1..v_combine.count loop
        dbms_output.put_line('Element ' || i || ' = ' || v_combine(i));
      end loop;
  END;
  /
  Element 1 = 1
  Element 2 = 2
  Element 3 = 3
  
  PL/SQL procedure successfully completed.
  
  SQL> 
  

  SY.

  Published by: Solomon Yakobson, December 14, 2009 11:19

• Open FPGA reference FPGA VI

  I'm learning the FPGA.  I have a few simple question.

  1. I tried to use the open FPGA VI reference configuration.  I selected the file bit on my PC, and I checked the run option VI FPGA.  Why I select the bit file on my PC?  The file bit is not supposed to be on my FPGA target?

  2. once I open FPGA VI reference, I fed to an invoke node, but it won't.  It is said that the sources and sinks have given different type, but he also says that they are both FPGA interface.  I'm a bit confused.

  Please see attached picture.

  jyang72211 wrote:

  1. I tried to use the open FPGA VI reference configuration.  I selected the file bit on my PC, and I checked the run option VI FPGA.  Why I select the bit file on my PC?  The file bit is not supposed to be on my FPGA target?

  Not quite sure what you're asking here.  A FPGA target has no local storage.  When you open the FPGA VI reference, LabVIEW support the bitfile on the FPGA.  The VI that calls open FPGA VI reference is one that opens the bitfile, the bitfile must be local to this VI (in this case, on your PC).

  jyang72211 wrote:

  2. once I open FPGA VI reference, I fed to an invoke node, but it won't.  It is said that the sources and sinks have given different type, but he also says that they are both FPGA interface.  I'm a bit confused.

  The FPGA reference on the Panel before you must match the configuration of the reference that you're passing to it.  Right-click on the front panel control and configure the FPGA reference to point to the same bitfile you open.  Better than that, bind the FPGA VI reference open to a Type definition and the place that the category definition on the Panel the Subvi front.  Note that if you do this, it works at the back of what you would expect.  Update of the baseline open FPGA VI changes the type definition; you never directly change the type definition.

• Good way to stop and run again a FPGA reference

  Hi guys!

  I have some problems when I try to stop, and then rerun an FPGA vi, I explain.

  I have two DMA FIFO to send data to the FPGA of the CPU and the CPU for the FPGA. When it receives data, the FPGA treats them and sends them to the CPU, and according to the result of the CPU does something. For example, it can be turn on LEDs or to rotate a motor continuous.

  But to do these actions, I have to use a "personality FPGA", i/o pins and LEDs appear to be managed by the FPGA core. So I have to close my reference vi FPGA in charge to receive data from the CPU, make my power on LED and then after raise again my FPGA VI once again, if I don't do LED blink or stay without effect rotation motor... But close and start again the FPGA VI creates problems when running, especially for the previous reading on the FIFO DMA awaiting... I tried to intercept errors on the FIFO to restart the FPGA VI with a good time but nothing... I am lost and I think Miss me something, concept, or something else.

  I can't share my code because I work for a company, but I would like to know if you have VI with this type of structure: a FPGA reference that must be stopped to allow interaction of material with the FPGA default personality then run again, all with good timing...

  I hope I'm clear, but if it is not the case, I can rephrase if necessary.

  Thank you very much for the help!

  Afghow.

  I do not understand why you need to change the bit file is loaded in the FPGA.  Why you cannot add code that handles the inputs/outputs to your FPGA processing?  Why do you still need to send data to the host (CPU)?  Just having the process FPGA data and change the output directly.

• Impossible to check the FPGA reference with "not a number/path/Refnum?

  How can I check if an FPGA interface refnum is valid?  It seems (LabVIEW 2009) that "Not a number/path/Refnum?" always returns true when connected to the output of open FPGA VI reference.  I write code that needs to be able to run without an FPGA for testing purposes, so I wrapped all calls to the FPGA in a case structure that I thought would run only if the FPGA reference is valid.  Turns out that they run ever, even when the FPGA reference is valid (probe shows it has a numerical value, and the FPGA VI is running).  I guess it's sort of similar to semaphore and appointment of references that have their own special function to verify the validity, but I do not see such a function for FPGA.  I have to cast to int and check if it is not equal to zero?

  
  

• FPGA reference questions between the station development and execution? 63195 error code

  I will do my best to describe the problem, I was see.  Note, I tried a few other messages that kind of touch on my problems, but they never seem to have a definitive solution.

  Background-

  I have 3 screws:

  VI 1) opens / runs the bitfile FPGA reference and stores the reference to a global file so that I can call the reference of other screws I need to do this as opposed to the opening of a new reference because I use the FPGA for digital communications and it adds about 100 ms to to open a new reference whenever I need to read/write in the target FPGA to host (100 ms are long in the) digital world!).  Some people use Shift Registers.  I finally called my whole army FPGA screws of TestStand to run a test automated, so it was easier to break up of my functions for open/close/read/write.

  VI 2) called the global reference of the file for FPGA, then going to a read/write node to change the settings of the target, then passes the reference out of the node back to the global reference of the file read/writable

  VI 3) calls close reference FPGA and the function is passed the global reference of the file.

  Question-

  I understand not why this method works fine when I run either of TestStand with station options defined for the development (not running) mode or when I open VI which calls these 3 screws individually in sequential order but IS NOT working when I try to run these screws individually (Run VI 1 - open-> write Ref to the global reference of the file-> Run VI 2 - read global file reference-> playback control function / writing-> error-63195) or when I have run in the same sequence TestStand but together with station for execution options.  Maybe I need to change the TestStand sequence to load all the modules at startup?

  Why the reference becomes lost when global failover between development and execution and why labview cannot drop keep the reference stored?  Is there a work around?

  Finally found a solution.  I do not understand why it is necessary during the reading of the FPGA and not what writing (in fact I do not understand why it worked at all) but I ended up changing the properties of the step in my TestStand sequence for the step calling my DTL_READ.vi to be properties-> Run Options-> Unload Option-> "Unload after executing the step.  That seemed to do the trick to get my test TestStand sequence to work in runtime.

  I still don't understand why this was not required when you run the same sequence in the design environment and why it is not when I call my DTL_WRITE.vi.

  The DTL_READ.vi and the DTL_WRITE.vi pass the parameter labveiw global.vi 'Reference FPGA VI"of a node in read/write.  I don't know if the root of the problem is in my host TestStand and LabView FPGA VI...

  Thanks for all suggestions from you guys!  I'm happy I work but I am still confused by the solution.

• Open FPGA reference fails to run

  Hello

  I apologize if this is covered elsewhere; I found nothing relevant.

  I have a fair size RT application that calls the vi FPGA reference open as the second point during initialization.  The FPGA is compiled and worked fine before with a simpler application of the RT.  When you run the program I probe the wires of the error as well as highlight the execution and the program is just stuck on that vi.

  The vi is configured to point to the FPGA vi in the project.  I tried pointing to the bitfile and the same behavior occurs.

  The goal of the RT is a sbRIO 9631 with NOR-RIO installed 3.5.1 (without scan interface).  I reinstalled it during my troubleshooting.

  So with that, any suggestions?  Otherwise, I can be on the phone with TOMORROW and will post whatever I learn.

  In the same vein, it would be possible that the user interface is simply not updated because you use too many resources on the RT controller. Especially with probes and highlight the running, the transformation of the network might be causing a problem. In the measurement and Automation Explorer or distributed systems manager, you can view the sbRIO here memory/CPU usage:

  http://digital.NI.com/public.nsf/allkb/8C7B655978C8ADFB86256AAE004AD261?OpenDocument

  I would try also to Flash the sbRIO then reinstalling the 3.5.1 drivers on the device and try again. If you had a different version on the target as 3.5, it may have been a fix that resolves this.

  Finally, try to have the FPGA vi to run when load/run when starting the crio by following these KBs:

  http://decibel.NI.com/content/docs/doc-3076

  http://digital.NI.com/public.nsf/allkb/BC513C2A0DC29C89862574BF0002B0B9?OpenDocument

  Thank you

  D Smith

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  Thank you.

  Original title: I use Windows 7 and I am not able to print several different images on a single page. The answer posted here from 8/11 includes a link that does not work.

  Hello

  Welcome to the community of Microsoft and thanks for posting the question. I've surely you will help find a solution on the issue.

  What program you want to use?

  We will try to print in a different way and check.
   
  Open Paint and then do a collage of different photos then save it then open it in their program and print.
   

  To print the image in Microsoft Paint, steps to follow:

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  With the help of paint

  http://Windows.Microsoft.com/en-us/Windows7/using-paint

   
  Hope this information helps. Please reply back with the

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  Yes. This is possible. IOM allow this.

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