Similar Questions

• With the evolution of the lines from outside the PXI-7831R problems

  I have a map of PXI-7831R and I am an envelope in return (for automatic test) to a port on a connector to another port. Connector 1; Port 0 to Conn 1; Port 1. I send a pattern on port 0 and receive it on a port, it works. I then change the port 1 to outputs and use the port for entry. I send the boss and that he is not encapsulated in return. On the 2nd or the 3rd try, it will work. (i.e. I send 0xAA get 0x02, I then send 0xAA and return 0xAA)

  This same envelope back work properly on the connector 2 ports and DIO connector 0. He is also working on a PXI-7813R connector/ports I use.

  Anyone seen this before? What do about it? What Miss me?

  I tried to put a period between where I put a port as output and dot actually sending. And I have a delay between when I send a port and receive on the other port.

  I found my problem. I had a few structures business wire connected to the wrong place. They were simply hidden by other structures in the diagram. It was just a coincidence that they're on the case where I was turning the inputs to the outputs.

  LabVIEW 8.6 can be helped with the cleaning diagram functionality. We use 8.5 since that's what we started with.

  Thanks for your help

  Joe v

• PXI communication problem of NOR

  Hello

  I use the chassis NI PXI-1042 q with NI PXI-8196 embedded controller, I couldn't contact my NI PXI PCB (NI PXI-5124, NI PXI-4472 etc.)

  Currently, I installed NI LabVIEW 2010, NI MAX 4.3 and WINDOWS XP operating system

  Concerning

  Raj Kumar S

  Have you tried to go down and retrieve the PXI cards?

  Another tip:

  The NI PXI-8196 RT is a RT controller where you can download and run your application in real-time. In other words, you have to develop your application in a Windows operating system and download your app in 8196 via Ethernet.

  You should see your PXI as a big cRIO with PXI cards.

  You can double bot your PXI (Windows or RealTimeOS). This link might help you understand your hard specifications:

  http://www.NI.com/PDF/products/us/2005_5483_501_101.PDF

  ARO

  Vincent

• question pxi_trig FPGA with multiple cards

  I'm trying to get several cards to control and drive the same pxi_trig line.  The goal is to have all the cards to follow the same trigger line.  When a card is said to occur, other cards should detect it.  I found a similar problem discussed here, http://forums.ni.com/t5/PXI/pxi-trig-problem/m-p/1013201, but I try to avoid having a master / slave relationship.  Again I want any card capable of steering the trigger.  If I understand that the problem has been resolved with the method "Set exit help", I don't see the expected behavior.

  Any help would be greatly appreciated.

  Hi Thatguy,

  It seems that what you're doing should work.  As long as you reference the same trigger, they will all use the same physical wire from the PXI backplane.

  I don't follow the logic of sense, though, but I guess what you're trying to do is to determine if this card tries to lead the line, while the value"Set out".

  One thing to note when the line is not used, it is drawn up.  I don't know if this could be what you see or not.

  What behavior do you see?

  Dave T.

• What pins to use to receive the data from the PDS ELITE RS485 with the PXI-8431/2?

  Hello!

  I use the PXI-8431/2 to read data from the flow meter PDS ELITE (Modbus RTU). Receiving data, the RS485 protocol request to terminals 4 and 5, but this configuration does not seem to work. When I connect the RS-485 converter USB of Microflex I get the data correctly, so somehow between the PIN lay and PXI this problem there.

  Can someone help me?

  See you soon,.

  Steven

  Hello Steven,

  I think that what was Hossein trying to send you is the following:

  How to connect and configure a device with RS-485 2-wire

  Can you also tell me a little more what you use to read the data? What environment. You have 2-wire or 4-wire Modbus RTU?

  Kind regards

• 1031 DC pxi star trigger

  Hello colleagues LV coders.

  I've looked everywhere and can't find the answer to the following question: How can I access a trigger in Star in a PXI 1031 DC chassis?  I know this must be through SLOT2.

  I currently have a micro controller PXI - 8102 SLOT1, an arbitrary generator (AWG) pxi-5422 the SLOT2 and a PXI-7954r FPGA with a digitizer 5761 nor in SLOT4.  I know that activitate the outbreak in Star, a "Timing and synchronization' card must be in the SLOT2.  Is it possible that I can use either the microntroller in SLOT1 or the Working Group in the SLOT2 for access to the relaxation of Star?  I think that the microcontroller will probably be able to reach, but what about the Working Group?

  Follow-up on issues is as follows: suppose that I am able to implement this Star trigger correctly, once the working group receives the signal to send its chirp 10usec by having the Star trigger go HIGH, is there a way of simultaneously to adjust the line of PFI0 HIGH in the Working Group and a time that the 10usec is completely sent to set the PFI0 on the BASS line in the generator of signals for usec then 90? This could be repeated indefinitely and the PFI0 line is used to control a switch via a cable.  In addition, this PFI0 of the GTS line will always be equal to "output mode".

  Thanks in advance a ton.  If I found the answer elsewhere, I'll make sure to update here.

  -Daniel

  The link "what GIS speeds. do my chassis PXI Trigger lines Support' really helped me to understand how triggers are connected in the bottom of the basket of the PXI chassis.  In my case, I need my shutter button to get to the e in 1 usec and thus the PXI Trig. Bus to get there.  No need to worry about the outbreak in Star for my application.  Thanks for the research!

  http://digital.NI.com/public.nsf/allkb/892204272FF2C0BE862575C500636AF6?OpenDocument

  -Daniel

• Synchronization of two SMU 6537 in acquisition mode

  Hello

  I need to use two SMU 6537 in parallel for a digital acquisition, their examples of clock is synchronized and running at 50 MHz. In the manual, I can't know is possible to correctly route connections through PXI background:

  -It seems that the path available only for export SAMPLING CLOCK in acquisition mode is 5 PFI, so no way to settle the two cards in a master-slave via the background.

  -I don't see or can use the background 10 MHz REFERENCE for synchronization, because it seems impossible through the DAQmx driver to deliver this line as input for the time base and trigger (it is not even in the list of possible signal entries).

  -The manual States that the maximum allowed value for an external time base is 50 MHz, whereas I need 50 MHz acquisition rate. I guess I should put in Sync synchronize databases internal time of the two councils through the background, but I can't figure out how.

  Any suggestion on how to solve this problem?

  Thank you, Piero.

  Piero,

  TO synchronize these cards, you must share the sample clock and a start trigger.  You should be able to send the sample for PXI Trig 7 line clock and use it for each of them.

  -Christina

• Deploy with fpga after change of chassis.

  Hello

  I'm running a project Veristand 2011 with an NI PXI-8109RT controller, a jury of NI PXI-7852R fpga and analog outputs 5 NI PXI-6733.

  For development, I used a chassis PXI-1000 b.

  Now, I have moved the system to a PXI-1045 chassis, and I can't deploy the project more.

  It gets stuck the "start of the deployment group 1", and after a while, I get a timeout error (-307672).

  The only way I deploy the project is to remove the FPGA of the nivssdf and remove the NI PXI-7852R of the chassis.

  Of course I need to map FPGA, then... why the project will not deploy with it?

  Thank you

  Matteo

  Hello Matteo,.

  The chassis of 1045 (and other PXI chassis with a large number of slots) have several segments of independent PCI bus along the bottom of basket.  By default, triggers are not shared between the segments.

  So, if you want to synchronize all your cards, one solution is to put all cards in the same bus segment.  If this is not possible, you will need to go to MAX and manually map PXI Trig 0 away from your card master sync everywhere for other bus segments.  For more information on how to do this, see the following document:

  Routing see PXI trigger in the bus chassis PXI crossover

  Kind regards

  Devin

• Problem with PXI SMU 4132

  I have observed 4132 PXI is sometimes load dependent. We were testing a specific device
  which is part of the bi-directional and when we forced a current through the device in the negative sense of the whole
  current is not available through a device (i.e.) when I force - 1mA through the device, I would see a 1mA through the device.
  However what we observe, it's only 0.5mA is available through the device. This happens only in the negative sense.
  2.) I have observed this behavior for a specific device. We tested the same device on keithley 2611 and they
  measure well. In my view, that the problem must be with the EMS.
  How much output impedance is present in this SMU? How can this problem be solved?

  
  

• Problem reading the PXI-2503 channels above 23 in mode 1 wire 48 x 1 Mux on Linux

  I can't get the above relay stations 23 in mode 1 wire 48 x 1

  % nilsdev | grep 2503
  OR PXI-2503: "Dev1".

  The topology is set on "2503/1-Wire 48 x 1 Mux ' via the following API, using the 'Dev1 '.

  DAQmxSwitchSetTopologyAndReset (device, topology)

  In theory this means there are 48 relay individual that can be read, however, fails the following:

  SwitchName = "/ Dev1/ch47.

  DAQmxSwitchGetSingleRelayPos (switchName, & pos)

  The error returned is:

  DAQmx error: relay name is not valid.
  Relay name: ch47

  State code:-200202

  who is

  #define DAQmxErrorInvalidRelayName (-200202)

  I can't get the relay station for foregoing relay 23 (/ Dev1/ch23)

  Which is the expected behavior, or is there a hardware or driver problem?

  When you use this switch in "1-wire" mode, we break essentially each (+) / (-) pair in their own channels.  Since this topology uses switches bipolar, only throw which individual terminals cannot be activated independently, another switch is introduced in order to decide which side of the switch is consulted at this very moment, (+) or (-).

  Instead of having 48 simple jet unipolar or bipolar, we have 24 bipolar single jet and two-way to decide what polarity we are referencing a single pole.  You can still use this topology in mode 1 wire 48 x 1.

  To switch manually using relay DAQmx controls, you need to specify the channel switch and polarity as Maggie mentioned.  When you call ' DAQmxSwitchConnect/Dev1/ch47/Dev1/com0', the driver knows that he has to close the relay 24 ch in more 'HLSELECT' AND "1WIRE" route only positive (effectively ch.47).

  The document NOR switches help contains a more detailed explanation of the topology if you access devices > NI PXI-2501/2503 >

  1 wire 48 × 1 Multiplexer topology.

• Problem sending trigger software through backplane PXI (chassis SMU-1082, SMU-6363 DAQ, SMU-6544-HS-DIO)

  Dear community,

  I am trying to implement a background basket (software) PXI trigger on a chassis NI SMU-1082 with LabView 2015 (32-bit) running on an SMU-8135:

  HS-DIO (SMU-6544) in slot 2,

  -Acquisition of data (SMU-6363) into the Groove 4,

  -Flex RIO (SMU-7962R + OR-6583) in the Groove 3.

  The trigger schema is explained in the attached file ' LV-PXItrig-HSDIO-DAQ - overview.jpg ".

  Scenario 1: written DAQ analog signal and sends signals trigger HS-DIO (software) through bottom of basket, after East of waveform of the complete signals to DAQ for acquisition.

  Scenario 2: logical impulse on an external port HS-DIO triggers signals HS-DIO, after HS-DIO waveform is complete DAQ triggered for the acquisition of the ADC by the backplane.

  In principle this breaks down to send a trigger of module A to B by PXI backplane. The SMU-1082 chassis has a bus trip with 8 lines (PXI_trigX, X = 0,..., 7) more a trigger in Star controlled the slot 2.

  I've linked to implement a software trigger, but I can't access the refreshing resource and execution, see the attachment. Other ways of implementation including the DAQmx Terminal / routine disconnect Terminal have not worked for me either. I am aware about the connection of trigger using the node property VISA but I can't make a trigger.

  Tips, comments or solutions are appreciated. Thank you!

  For scenario 1, you want to trigger the HSDIO acquisition to begin as soon as the analog output DAQ starts?  You can use DAQmx Export Signal to send the trigger for the start of one of the lines from the Trig PXI backplane. Then, you need to configure your HSDIO acquisition to use a trigger digital beginning on the same line of trigger. Take a look at the example of the "Dynamic hardware generation start trigger" in the Finder of the example (help > find examples)

  For scenario 2, looks like you do a dynamic unit HSDIO generation when a digital trigger arrives on one of the PFI lines. Once the build is complete, you want to send a trigger for the DAQ hardware to begin sampling. If this is the case, you again use a trigger to start material in your task of NOR-HSDIO, as you did for scenario 1, but use external trig line as the source, rather than the bottom of basket. There is no case of material when the build is finished, but you can use a marker in script mode event instead. The example of the Generation with dynamic event marker' in the example Finder gives a good starting point for this type of operation. You'll want to set the output terminal for the event to be a line of backplane trig, and then tap the DAQmx to start on the same line trig trigger.

• Problem of delay time PXI-5105

  Hello

  I'm running the PXI-5105 (@ 60Msa/s/ch 12 bit 8Ch) using the attached VI. I put it to trigger off channel 0 to 1V.  When I put in a sinusoidal waveform of cycle 5, it seems that the scope triggers too late and I only see 4 of 5 cycles.  I confirmed this by generating a sinisoid of increasing amplitude across a PXI-5412 and again once the waveform has been truncated, as if there is a delay after that relaxation hit.  (btw, I have an oscilloscope running in parallel and the waveforms appear perfectly here)

  Why this is happening any help would be really appreciated.

  Thank you!

  Actually - problem solved.

  When I played with him I had inadvertently set it to DC coupling.  Coupling AC fixed.

• PXI-5412 access problem

  I have a PXI chassis which has a function (PXI-5412) generator.  The function generator exhausted at work but acts after that I reinstalled the drivers to solve a problem.  It does not appear in the category DACmx or traditional daq.  Using the name of the instrument (PXIx::yy:INSTR) will not solve the problem.  Got prompt "signals of NOR detected all the generators are used by other processes and are not available for the FGEN soft front" when I try to use the or-soft front panel for test - nothing else is running.  However, when I took the PXI-5412 out and put it in another location everything would work.  I tried to reinstalled DAQmx and niFgen several times but it does not solve anything.  Help, please.  Thank you.

  Here is some additional info:

  LabVIEW 7.0, Windows XP, niFgen 2.4.0, DAQmx 8.0.1

  SB

  Hello

  I had the problem of the road.  I took the PXI card, use pliers to pin the side wall of the connector bottom of basket and it works.  I don't know exactly what PIN because of the trouble, but there must be one (or more) pins outside the connector of the PXI-5412.  I guess that I rejected question commitment pin a little too early in the game.  Thanks for help.

  SB

• PXI-8196 connection problem: plugin not installed

  Hello OR:

  The PC in interaction with our NI PXI-8196 (1052 chassis) has recently had a hard drive failure, and I had to reinstall all our LabVIEW software and live custom on a new host. The software is running, but I have problems with connectivity to PXI. PXI is recognized to the MAX, and everything is accessible (ladders for our load cells, etc.). But when I open my project to a labview VI, I can not connect for PXI. It has a yellow triangle with an exclamation mark next to it, and when I right click, the error message indicates that the plug-in is not installed. I have a CD that seems to have the PXI drivers on it, but after the installation, I got the same problem.

  I wasn't the one who originally this system connected to the network, and I cannot find documentation to get back up and running. Any help would be greatly appreciated!

  Eric

  So I solved my problem with the help of my local applications engineer. He pointed to me and made sure that the software on the PXI system synchronized with the host computer via the MAX add/remove software menu. I noticed that the version of the RT software on my host was older than the version on the PXI system. Not sure why this happened, as I had already installed the most updated version. Maybe he got more written in my flurry of facilities. So I reinstalled the RT 8.2 module on the host, and now everything works. Thanks for your time, Robert.

• Analog input problems using PXI-6232

  I tried to solve this problem for a while now without a bit of luck. Solution suggestions are welcome.

  I use a PXI-6232 with LabView 8.5.1 to accept signals analog several of my sensors. Based on the signals as a PWM signal is generated and the output using PXI-6713.

  Some of the analog input signals have spikes in them, which occur at all times during the tests. I watched the same signals on an oscilloscope - without crampons. I change my hardware configuration, and the spikes still occur in the same places. It seems that the program makes some resets resulting in measurement errors.

  I have attached the VI and a JPEG of measured inputs.

  Thanks in advance

  Concerning

  Vadim

  I was first confused of your time scale but it seems that these spices occur every 20ms (not s) what to a line 50 Hz noise due to switching power converters (or a diode without compensation bridges )

  Another clue was the measure of the scope. While using the application scope, you opened a groundloop so the spikes because of the dI/DT through the groundloop are another way to get around.

  So I'm pretty sure this isn't data acquisition (in this case) this is your configuration.

  Provide a cleaning (low R AND L low) path of power (keep them close and twist slightly if possible), add a filter to down the dI/dt, identify the ground loops.  (Use your scope with a little as a sensor at the entrance to reel and catch magnetic fields can open eyes)

  THEN to clean the last ears (on the acquisition of data) to get the last ppm use selfs