Synchronization of two SMU 6537 in acquisition mode

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  Alessandro

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• Synchronization of two inputs frequency meter with several analog inputs

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  I'm relatively new to LabVIEW and I'm trying to collect data from multiple sources with calendar sync on the acquisition, but I can't understand. My problem is that I have two inputs frequency meter, an optical tachometer reading one pulse per revolution and a max flow meter machines with a 12000 k coefficient. I can't find a way to synchronize the calendar with my multiple analog inputs. I tried to first get the speedometer to synchronize with the analog inputs following the example linked here. (https://decibel.ni.com/content/docs/DOC-10785) So far every time I run it I get an error on the DAQmx read timeout or an error "several sample clock pulses have been detected" (see image).  It seems if I slow the way to down to say 10 hz and make sampling rate ensure that the tachometer signal is more than 800-1000 rpm (13-17 Hz) before starting the VI then the program will run without error until the ROTATION speed is below this threshold, then the "sample Multiple clock pulses" error occurs.  The code is attached below.

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  Chassis cDAQ-9178 with NI 9401 for both counter inputs and NI 9205 for the analog inputs.

  Thank you!

  Richard

  I know the error requires to restart the task at least (this particular error puts the material in a State that cannot be recovered from during execution of the task - I've been down this road before) but I'm surprised that you would have to delete and re-create the task altogether.  And then I had to do this to workaround other questions in the past.  It is awkward and should be considered a bug, if this is indeed the behavior.

  Honestly, regardless of this bug, the way the material dealing with the situation of several sample clock edges makes measures of sampling frequency clocked essentially unusable for purposes of synchronization (in my opinion anyway) If you encounter a more slow than your sample clock rate.  You are supposed to be "synchronization" of the measure, but it really no longer applies if you have to restart the task over and over again (if you must delete it or not).

  Workarounds can get kind of creation (which isn't really a good thing).  For example, you can configure a measure of implicit frequency to keep a buffer of frequencies and use a leader board task (source is the frequency signal, sample clock is the sample clock HAVE) to establish a correlation between the index of your buffer of frequency for singing HAVE sample clock.

  Best regards

• Synchronization between two periods loops FPGA

  First of all, I appreciate the forums here and have read a lot of interesting topics. This is the first time I can't solve it with research and I hope for your entry.

  Information:

  I'm using LabVIEW 2009 f3, PXI-1033 with the PXI-7813R.

  Problem:
  In my FPGA program, I have two loops, where you need to run as fast as possible (has) and the second just quickly (B). Has turns 20 MHz to 40 MHz and B . These are for the two loops limiting speeds. B cannot run faster and Has should not run more slowly.
  Loop has captures the sensory information and integrates data as many loops as indicated by the user. When completed, please send a trigger to B, which calculates the new position information and sends it to the machine. Only at certain times, B must achieve something and said nothing to the rest of the time.

  I thought of two ways, but doesn't work for me.

  (i) with the help of a Boolean trigger. As in a loop, the Boolean value of A can become true and switches to the next loop to false, B is not capture all the triggers and a 50% chance of getting the triggers and isn't perfectly synchronized.

  (II) using the occurrences. Sounds very interesting, but these are prohibited between the periods differently loops.

  I played with many scenarios, but may not understand proper. Someone at - it suggestions?

  This seems to be a fairly simple producer/consumer scenario.

  I would like to use a device worn FIFO to transfer data from the loop of producer (top) to the loop of consumer (bottom).

  Depending on how often the producer generates data (each cycle or every nth cycle?) the case around the write FIFO structure will allow him to write only when your requirements are met.

  The consumer loop reads the FIFO with a timeout of '0 '. When the FIFO is to expire, the consumer runs to the case which does nothing. When the FIFO does not expire, who processes the data and sends it to the side of Windows runs.

  In my example, I used 2 structures of cases to illustrate the two different modes. In your code, you must use a single structure of matter.

  There is no advantage to set a loop "sleep", even if no data exists on the FPGA. Because you are running in hardware and the non-profit CPU cycles these loops can operate simultaneously at no increase in the latency of a

  

• synchronization of two loops for...

  HII...

  I am using two loops for and I want each iteration for both loops start at the same time...

  in fact I want to sync between these two loops...

  so when the each iteration of the two loops will start at the same time then these will be synchronized...

  also if a loop takes more time in an iteration the other loop should suspend until the end of the iteration of the other...

  please me... thanks hlp...

  Hi samir,.

  two options:

  1: when both FOR loops should have same time iteration why not just put all the code in a loop FOR?

  2nd: when 1 is not possible/wanted, you can use a notification utility. Set the notifier early iteration of the first for a loop and wait for the signal in the second loop...

  3rd: use call loops and synchronize them...

• How to use the modules of the series and two different bitrates in FPGA mode on cRIO 9075

  Hello

  I have a project with modules namely NI 9227 (module 1) and NI 9234 (2 Modules)

  The project is running and I use the file writing PDM and found that two channels is in the TDMS file while I download the file using FTP the cRIO.

  1 - my quesition is the addition of a second rate in the FPGA?

  2 - Why is it TDMS connect 6 channels and 4 channels?

  Thank you

  Attached to the project with two screws

  Hello Ihab,

  Sorry for the late response here; just saw this message! If you want to keep synchronized modules then definitely stick with the master configuration and slave for your two modules. Note also that you can taste a little faster with the NI 9234 as your master module (since its time base main internal is 13,1072 MHz instead of the time base of the 9227 12.8 MHz).

  Also, see the tips and information in our troubleshooting guide for the synchronization of the series C with LabVIEW FPGA modules:

  http://zone.NI.com/reference/en-XX/help/373197D-01/target6devicehelp/sync_acq_multiple_modules/

  I hope this helps!