Risk of static conditions of race FPGA

Hello

I'm fresh off a LabVIEW FPGA course and I feel have a decent understanding of him, but a co-worker on a project we start is push me for answers before I had the chance to 'play' with him.

The questions are:

1. How do you deal with racing conditions?

2. How do you deal with static hazards?

My first response was I think that LabVIEW "will be on it', that data-driven paradigm of"wire"will ensure that the race conditions occur, as long as I'm not using local variables or write to the same control/indicator, in which case I'll have to consider race conditions in the same way I old No LabVIEW FPGA. Static hazards, never heard mentioned in connection with LabVIEW, so once again I assume he took care of "behind the scenes"?

The application is the streaming of data to a NI-SMU-5644R and do some calculations embedded FPGA before streaming to the modulator if it has no effect.

Thank you

As long as you correctly follow the stream, you won't have a race condition.  But it's something to be careful.

I don't never heard of static hazards being an issue with LabVIEW FPGA.  One thing that does NOR is there buffers for each clock cycle.  This will keep the static hazards away.  Inside of a loop single-cycle timed, these pads are removed for all within a single cycle.  I don't know what OR with these, but I've never heard of him being a problem.

Tags: NI Software

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