synchronization sequence FPGA structure problem

Hello

I use a sequence structure in a VI on the FPGA to a cRIO-9073. The time of each sequence is active is determined the number of times defined by the user. In theory, each sequence should take the same amount of time, but when I check it with an oscilloscope is not the case. The signals produced do not have the same cycle. When the number of ticks is equal to 1 in the VI on the FPGA, I receive a frequency of 400 Hz, approximately to the blockwaves outputs. I expect it is much higher since the FPGA runs at a frequency of 40 MHz clock. Why the frequency of the signals so low and why isn't the market factor the same for all signals?

Best regards

Beurms Jasper

Several of your synchronization on the FPGA screws are set in milliseconds, not ticks; in all cases but cases #2. I hope that this is the problem. Double-click the VI and change the setting. In fact, why have a timer to wait in any case? Just pull it outside the structure of the case and have 1 instance of the VI in the while loop. Also, whenever I see the files named * _ it probably means that you do not use the source code control. I would highly recommend.

Tags: NI Software

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