CRIO and WSN

Similar Questions

• time real cRIO and confusion of FPGA

  I'm confused on the use in real time or FPGA.

  I learn from training material, you use cRIO with FPGA and real-time, you have two

  synchronization means: one is the analytical engine, another is calendar FPGA. However, the frequency of synchronization

  real time is limited to 500 Hz, see attachment.

  I wonder, if I want to acquire samples using 5 k rate of real-time data acquisition card

  system, such as cRIO and sampling interval is 1 Hz. That is, using a timed loop which is 1 Hz and inside

  the loop, can I use DAQmx to acquire waveform using5k rates?  or I have to using of FPGA to acquire waveforms

  Whe I want to acquire signals with greater than 500 Hz rate?

  cDAQ is not an FPGA, but use DAQmx.

• How I develop on a crio and deploy on another

  How I develop on a cRIO and deploy on another?

  I have developed a cRIO application and test on an another cRIO before deployment on many other cRIOs.  (See image below).

  

  I used to do this in real-time systems: develop in our facilities with our materials and test it on their development on the site of the client system.  But with the cRIO things are a little different.  In the Project Explorer window, I host (my computer) and the target (cRIO Lab).  I tried the following:

  • Connection: disconnect the cRIO Lab (via the Ethernet connection) and the cRIO of customer connection and then discover the new cRIO in Project Explorer. This works.
  • Copy VI & variable: I copied the same file under the cRIO Lab structure in the project for the new cRIO Explorer. I did this by adding a VI and a variable - the same ones on the cRIO Lab shared library. It seems to work.
  • Running or not: the problem is when I try to run it because it looks for variables that are shared on the old cRIO.

  System Specs: LabVIEW 8.6.1, cRIO 9074 w / various modules, configured in scan mode and to be deployed as an executable

  What is the best way to copy an one cRIO to another project?

  Hello

  First off I will say that it is the problem more beautiful and informative that I saw.

  Secondly, you should be able to do the following:

  -instead of adding the two targets to your project, just go to the properties of the target (target of click right, select properties) and change the IP that you are testing on. That would be the simplest and cleanest method.

  - Otherwise, in your configuration, when you port code from one to the other cRIO, don't forget to right click target and select deploy all. You must rebuild your application as well.

  Please let me know how these suggestions work out for you.

  Kind regards

  Anna K.

• cRIO-9074 ethercat with a switch/hub between the cRIO and slaves

  Hi, I have a cRIO9074 I'll use 7 JVL EtherCat Mac800 motor control.  Engines are fairly spaced, so I use a switch of CU2005 EtherCat Beckhoff 5 ports between the readers and the cRIO with 2 motors in series on three legs and a motor on a port by itself.  My problem is that labview will not find all engines unless one of the ports on the switch motor is plugged, or a line of engine is connected directly to the port ethercat cRIO.  He has no problem see two engines on the same line, it just will not see one of them if more than one line of motor is connected to the switch ethercat.

  Thus, HALP!

  
  

• VeriStand cRIO and XNET 986 x

  Hi all

  I find a few KB and the tutorials that explain this cRIO Modules XNET CAN 986 x are supported by Veristand.

  I use this tutorial to set up my Veristand project: http://www.ni.com/tutorial/14706/en/

  However, I have a problem. When using 986 x it says I hace to select the bitfile I just compiled in 986 x Configuration page.

  How should I develop a LV FPGA VI who manage 986 x for Veristand? Is there any kind of example or model to follow?

  I have really not uderstand how my FPGA LV should look like...

  In this tutorial, it just says that I need to create an empty LV FPGA VI...

  The trick is in the project settings. The module communicates background aka the analytical engine. Empty vi compilation will add this underlying mechanism.

  If you go to help - find examples and research of 9862, there is a project called CompactRIO.lvproj OR-XNET CAN example. You can use it as a starting point.

  C:\Program Files (x 86) \National Instruments\LabVIEW 2013\examples\nixnet\projects\NI-CompactRIO\NI - CAN CompactRIO.lvproj XNET XNET

  Jiri

• cRIO and smart camera working simultaneously

  How can I get my smart camera to operate their screws simultaneously on the same ethernet with a hub port? It gives me an error if I run the smart cameras and Crio VI.

  double post, already answered here

• cRIO and synchronization with PC with 1588 on Ethernet card

  Hi all

  I want to synchronize my cRIO with my Windows 7 computer.

  -Is it possible to apply the Protocol of 1588 in two materials using the PC as master clock and cRIO as slave?

  -Where can I find examples?

  The goal is to acquire temperatures via modules OR-9212 and cRIO to communicate to the PC by putting in place a lighter version of the JENA Protocol.

  In the final architecture, I could have multiple cRIO.

  Requirement:

  Don't use NI 6682 H card or other

  Can use the NI Sync module

  Use on the borad ethernet card

  PC running Windows 7 with LV 2013

  cRIO-9067 under LV - RT 2015

  Hello

  This is a documentation on the implementation of the NTP Protocol on cRIO running Linux RT and the host computer with Windows

  -Installing and configuring NTP on Linus RT

  - How to configure a time server NTP on Windows

  Adrien

• Strange error with cRIO and scan Mode

  I'm scanning two modules cRIO on a controller of 9012 + 9112 bottom of basket 8 channels in scan mode, and I call the function 'read the Variable scanned '.

  I see this error, each a few scans:

  Error -2132869099 occurred at Property Node (arg 1) in PolymorphicModuleScan.vi:7->sampleData2.vi->ZDAQ_cRIO_Target_Main.vi
  
  Possible reason(s):
  
  LabVIEW:  (Hex 0x80DF0015) A deployment transaction is in progress.
  

  The search for this error on NI.com gives no help at all.  This is the first time I see this (I've been running this code for some time without error).  All software is since the dev of August 2011.

  Resolved: I was calling the function "Get the Period.VI of Scan" scan at 1 Hz.  This seems to have caused the 9205 (not the 9237) produce this error.

  I removed the call to the offending function and this has solved the problem,

• Why do I get error 66 with cRIO and STM library after 6 hours

  I have a RT (for the cRIO-9004 controller) software and a host software (on my development computer) which Exchange data through the STM library. Everything works fine, but after about 6 hours, the host stops with a message 'error 66 in STM Read Msg.vi'. Why does this happen? I use LV 8.2 and the STM 1.0.32 library.

  Thanks in advance.

  Hi all,.

  would it not possible to send your project RT together in order to test it. Make sure that the SubVIs are included. Thank you! Perhaps one of the possible reasons for your error is that your VI uses 100% of the capacity of the CPU for communication over TCP/IP breaks down due to a leak of resources, because the priority of the screw is higher. Check the use of the CPU resources when running.

  Concerning

  Greg

• problem with timing cRio and FPGA

  Hello

  I develop software for measure the position of a device using some quadrature encoders.

  What I do uses the FPGA interface to acquire the position, then send usign real number of the meter to a host pc to create a data file. In the RT environment, I create a table with the position and the time that is acquired and using shared variables I send the array to the host PC.

  But I have a problem with the sync. The sampling time is unstable, I use a timed loop to control sampling but after some acquisitions, data sampling period begins to increase, as you can see in the image of attachment file. In the attached picture, I used a period of 250us and after some time gets twice and 3 times longer before you clean the table and begin to create a new table, during the period in 250us again. so the problem is that I should get a stable period in 250us instead of these steps in growing period

  You use the table of construction to add new data points? I suggest to use the function "Initialize the array" and "replace the array element. It will reduce the time it takes from the table of the construction.

  I can't open your code as I have LabVIEW 2010.

• I need to change a FPGA.vi that has already been deployed on a cRIO and runs at startup.

  What is the best way to change the program without changing its function.  I just need to say if the cRIO is online or not - of a host.vi with a FPGA reference (I tried to use the LED FPGA as an on/off control switch) without success).  I have to stop or suspend the operation of the existing FPGA.vi to do this, or there at - it an easier way?  Can I use the same FPGA in another window for project?  I'm running 2009 LV a NOR-9012 controller with Windows XP Pro with a chassis OR-9112.

  
  

• cRIO and 9234 modules do not work or communicate via fpga with accelerometers, fpga, connected to the real-time application is also related to shared variables related to modbus slave

  Hello

  I have a compact rio, which has a 4 way frame this chassis is the three modules of ni9234, they are related using FPGAs for application in real time, then using shared variables in the low-speed loop associated with a slave modbus to communicate with the domain controllers, the nor 9234 accelerometers linked to them with option ac coupled iepe on c modules , my problem is the real-time application seems to work well even when power loss occurs it restarts without problem and the fpga written hard disk portable bin files very well, but without an accelerometer connected I get readings of low noise as soon as I connect an accelerometer to one of the outputs 10 it just goes to a fixed number (0.03125) as soon as you unplug it again He returned to readout noise, I ran a scan on the modules and get only a spike when I connect or disconnect the accelerometer, I tested voltage at the pins on the module and I get 22 volts CC which makes it more likely that the material is not the problem, but software is perhaps the cause to hang up, I join the project and files for your perusal. I also realized a new project which, in mode directly linked scan has the module entry in the shared variable and the scenerio even once again. Help would be appretiated.

  Thank you very much

  Jason

  Whren using waveform with the 9234 acquisition, we recommend the following FPGA and RT model.

  http://sine.NI.com/NIPs/CDs/view/p/lang/en/NID/209114

  It can be extended as a datalogger with:

  http://zone.NI.com/DevZone/CDA/EPD/p/ID/6388

  or using shared variables combined with the analytical engine

  http://zone.NI.com/DevZone/CDA/tut/p/ID/9851

  The FPGA in all this, as well as the framework of RT have used successfully by 1000s of users.  I recommend giving these a try.

• Series communication between computer and cRIO

  Hello

  I am not new to Labview or cRIO programming, however, venture in for my first try at the serial communication.  I have a controller (not original NOR) that sends data over a serial RS232 network I want to open a parallel session to the data that I collect with a cRIO.  Before we get to integrate, I try to test with a series, my computer cable and hyperterminal communications and the serial port cRIO.  I followed and validated exploitation and drivers with the following text:

  How to do a loopback Test series
  http://www.NI.com/white-paper/3450/en

  However, when I try to use the following example, I get nothing:

  Transfer data between cRIO and host series
  https://decibel.NI.com/content/docs/doc-3816

  Any ideas on where to start?  I appreciate very much all the advice.

  Thank you.

  I have confirmed that it is a right.  I'll try a null-modem cable.

  Thank you!

• CRIO 9853: Why the mask is required to send and receive extended frame CAN (J1939)?

  I develop application RT who communicate with device of CAN frames extended through CRIO and 9853 CAN module with J1939 Protocol.

  I look at Protocol J1939 example of reference to help me in my project.

  Everything works fine, but I want to know why when I use the 9853 Module I need to use the bitmask (AND 0x1FFFFFFF to READ and OR write 0x20000000)

  As you can see on the example of OR... (to WRITE)

  

  Therefore, use both mask the good CAN Frame ID on the network?

  He's not blok me... but I would like to understand why I need to add this code...

  Hope someone will have the answer.

  Roman

  Playback uses the 30 bit to indicate whether the ID is standard or extended. Otherwise, if you have received ID 0x0000000A, you don't know if it was std or extended. For higher numbers (> 11 bit), it's obvious, but the flag is set, without worrying if you don't need several branches.

• cRIO thanks the Module NI 9237 bridge in the Interface of scanning and Anti-Aliasing

  Hello

  I have questions about the use of a Module NI 9237 bridge with CRIO and its use in Scan Interface mode. The manual speaks the data rate of the module, and a (n) parameter that can be set to adjust (to a minimum of 1613 Hz) which in turn puts across the module built in anti-aliasing filters. It seems (but not explicitly stated) that this data rate setting is available FPGA programming mode.

  Our application is currently running in mode Scan Interface, so my question is what is 'throughput' module (and therefore anti-aliasing filters) mode Scan Interface? And, if we have the analysis period the value 10msec (100 Hz), y at - it no filtering of the anti-aliasiing of software provided automatically by scanning interface itself related to the period of scanning? Or all the anti-aliasing extra something that we must build within ourselves? I looked at the example provided with Scan Interface and there is nothing more.

  I don't understand about anti-aliasing, just need to clarify what is happening for this specific module mode Scan Interface.

  Thank you

  Andy

  Hi Andy,.

  I had to have a quick sleep on this night to get my facts right, hope that the delay was too long!

  The minimum data listed in the 1613 samples/s are due to a forumla that uses the internal time base that is fairly well explained on page 20 of the Manual. The sweep period did not affect the rate of data, or to activate the anti-aliasing filter. My previous post was wrong in that sense, apologies!

  This page helps explain mode of scanning pretty well too, but the best way to explain it is that even if the frequency of the module can be attached to 1613 samples/s or higher, the compactRIO will collect only 1,000 of these samples a second, or in your case if you are using a rate of 10ms loop, 100 of these samples of 1613. The anti-aliasing cut will be based on 1613 x 0.45 as you said and so will be 725Hz (not based on the rate of loop as I mentioned incorrectly)

  In this case with these modules it is probably a good idea not to use a period of scanning slower than 1 msec for the reason you said - if you're worried about oversampling you can always you decimate readings in the software afterwards to take each readings from 1 to 10 (this page explains how do with an eerily similar situation!)