FPGA: Change the sinusoidal signal generator

The sine wave in the FPGA palette generator, that's what I need to do
but he can't exit do 'cosine', which is outside of 90 degrees. I need 120
degrees. To avoid discouraging, I opened the façade on the sine wave
Express VI generator that turned into a normal sup - vi. I changed the
a digital constant corresponding to 120 degrees out of phase, and the name was changed
of the output pin.

The module will not compile. First mistake was a wire that was a type of variable, the
Fix suggested to check a box for pre-allocating did not work so I made the table
the length constant of 1024 (that is, it is supposed to be). Following error was
that one line of vhdl file was too long (32 k characters for a specification of length 4 k max
characters).

Just for grins, I put the original VI Express return with the release of cosine and
It builds correctly.

There was a big damper on the modification of the vi. However, I didn't know that
simple conversion to a subvi and the tweak of a constant value would break.

Is it possible to get an updated the express vi for this application, or advice on how
changing the text that is there? The compilation breaks mainly online VHDL
length associated with the range of 1024 points.

I can roll my own generator of sinus by using some examples, not a big problem but
It will cost you some time. Another option might be to run two generators of sinus
and specify a different phase, but I'm not convinced that over time they
will be exactly synchronized. Change the Express VI is a much better
option.

Thanks in advance,

Bill

I discovered the hard way that LabVIEW 2011 has no records. After reviewing various options, I settled on the FIFO. The code presented here works well, but it is not save space on the FPGA to the wire using two generators of sinus with a phase difference in hard on one of them. For now, I'll use two sine generators, if this turns out to be unworkable in practice due to the relationship of phase adrift, then I'll look at it again.

The frequency and phase of the compensating controls are fixed point numbers formatted in zero whole bit and a 32-bit word. Bed down while the loop is synchronized with the loop timed by the FIFO, FIFO of 18 ticks timeout is two more than the 2.5 MHz in a loop which is a ditch-16. The IF block in the lower part, while the loop cut update control up to 10 KHz, 60 Hz sines more quickly.

Great experience, thank you for the help.

Kind regards

Bill

Tags: NI Software

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