HDL node settings

I am a beginner in VHDL, but... is there a bug here in LabVIEW?

In the configuration of a node of HDL to window, I selected the following settings:

X name:, Branch:, type: bool, length: -.

Name:, Branch:, type: [bool], length: 0.;

Name: Z, direction:, type: bool length: 0.;

LabVIEW then generates:

hdlnode of the entity is
generic)
13 kHz: Integer: = 40000000;
InSingleCycle: boolean: = false
);
port)
CLK: in std_logic_vector;
Reset: in std_logic_vector;
enable_in: in std_logic_vector;
enable_out: out std_logic_vector;
enable_clr: in std_logic_vector;
X: in std_logic_vector (downto 0 0);
Y: in std_logic_vector (1 downto 0);
Z: out std_logic_vector (downto 0 0)
);
end hdlnode;

I'm confused why LabVIEW has implemented X and Z as vectors. This does not seem right, because:

X name:, Branch:, type: [bool], length: 1

and:

X name:, Branch:, type: bool, length -.

both produce exactly the same VHDL code.

Why must LabVIEW behave this way?

I expected, LabVIEW to generate something like:

X: in std_logic_vector;
Y: in std_logic_vector (1 downto 0);
Z: out std_logic_vector;

Thank you
Mark

A CAR is generated?

Tags: NI Software

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