Outputs FPGAS do not operate in loop with derived quick clock

With the help of an map of RIO 7813R PXI with a controller OR in a PXI chassis (the way EITHER!). I need a 10 mHz reference clock. So be lazy I tried using a clock of 20 mHz derived with a timed loop, inverter and registry change, no joy: the output was reported sorting. To verify that I plugged two outputs, ensuring that one of them didn't jump. Then I used a loop timed with the clock of 40 mHz by default and a more complex arrangement to divide by 4, alto: it works. Why?

Thank you for any input,

Bill

I looked your PDF and tried to recreate your application LabVIEW 2009 and 20 MHz single-cycle timed loop worked flawlessly.  I have connected physically exit DIO to DIO another I read in a loop of 80 MHz and measured a clock of 10 MHz.

What version of LabVIEW and NOR-RIO do you use?  If you right-click on the OID in the project and select Properties, data, and both allow the value "Never arbitrate" and have a sync 1 register?  I don't think one of these parameters will be serious, but it could be one of the differences between our applications.   Are you sure that the loop of 20 MHz is running?  (EID will be tristated until the I/o node runs.)  What did you derive 20 MHz clock of?  Can you post your project and VI?

Tags: NI Software

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