Problems with mathematics at high speed on FPGA

I'm new on fixed-point numbers and math at high speed on the FPGA. I use the 7962 with 5751 adaptation module. I am writing a few simple codes to convince me that I understand what I do before writing code more complex. I wrote a simple code to divide two numbers and then multiply the result with one of the original numbers. The block diagram is shown below.

Looks like that the fracture is not working properly. But the multiplication always gives zero, and I can't understand why. A typical result of the façade is illustrated below.

If I remove the divide, the multiplication seems to work fine. Any idea on what I'm doing wrong would be greatly appreciated.

After more than a day of scratching my head, I realized that one of the entrances to the multiply function is always zero, because it is read 52 cycles later (i.e. when the structure case is false). To resolve this issue, I added a node back feed, so that the data is made in advance and are available to the function to multiply once the function of the line ends. I have attached a picture for those interested / with similar problems.

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