Synchronization of signals on my SBRIO problem

Hi all

I need some advice on how to complete my project.

I need to send a 32 bits of data to my unit test with the following parameters. CLK + FS + and +.

The clock runs at 4 MHZ. The FS + sends a bit length 33 of high for the treatment of the data signal, and in this context, I need to send my 32-bit data.

What I did is I created 3 loops as shown in my diagram.

1. the first loop is a loop timed to generate my clock pulses. I run at 8 MHZ with the low and high signals in loop rotation.

2. the second loop is for my frame sync signal using the rising edge of the clock over an external trigger (SEND DATA) to start the sequence. It has two red WAITING to the 0 graduation and 330 ticks (by tick is 25ns).

I have compiled up to this version of the code and run it with all the problems. I was able to generate the signal FS + 2ns after the clock rises and is to have cycles of clock exactly 33 in length.

3. the third loop which is I'll have trouble at this time is designed to loop data. I also used the pulse of the clock and the external data to start the sequence. I used one signal to WAITING to delay the start of the data by 1 clock cycle and use a loop for send data from 32-bit to 250ns (10 ticks) per line.

The problem is that I do not get the result I want. The departure of the bits is always erratic and not 1 clock cycle of delay that I hoped. Also the first bit is much too small for the 250ns.

Can someone tell me where I'm wrong? Is there another way to address the issue?

Your help will be greatly appreciated.

As a short response, I would recommend combining the three sets of loops in a single state machine.  All three loops are intended to be based on the field of derivative 8 MHz clock.

As a longer answer and to explain the behavior you see... the time of the present code is assigned by the data through the areas of the clock.  The details are in this help message LabVIEW FPGA: implementation of multiple clock domains with the overcoming of the areas of the clock (using a tunnel in the field to clock 8 MHz timed loop to the domain block diagram clock 40 MHz), LabVIEW is obliged to implement a hand shaking algorithm to maintain the integrity of the data.  This shaky writing consumes FPGA (logic cells) tissue and takes 25ns several clock cycles to run, as well as creates unwanted delays.  In addition, the third loop cannot guarantee that code data will trigger off the same synchronization signal as the second for loop because of the handshake that occurs for the data to pass through the loops of 8 MHz.

I would recommend that base you all of the communication out of a single loop timed in a configuration called a state machine.  Essentially, timed with a looping structure business inside, where each picture of the structure of the case is a different State.  Breast of a timed loop state machine, does not have the 'wait' function, so the delays must be implemented with a 'status quo' State which is repeated N number of times to match the time required.  The following link leads to a state machine similar to the SPI communication that would be a good example for the implementation of this communication: Example of SPI LabVIEW FPGA.

The example above implemented the following communication scheme, which seems pretty close to what you implement:

This code is a little more complicated than what may be absolutely necessary to your application, but it is an excellent example of a scalable & flexible of the notion of core implementation (this code can easily be migrated to new hardware targets or add multiple replicated or modified communication to the same architecture protocols.)

See you soon,.

Tags: NI Software

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