Stream FOR FPGA

Similar Questions

• How to implement point filters fixed for FPGA

  Hello!

  I am applying the bandpass filter Butterworth for FPGA.

  I managed to develop filters of fixed point that suits my needs, but I don't know how to implement on a table in a project after the FPGA code generation. I tried to understand it in the examples, but I was not very successful.

  My time to finish what runs, any help would be really appreciated...

  Any suggestions?... some examples?

  Thanks in advance

  I've already done that and solved the problem.

  In any case thank you and have a nice day

  Ljubica

• Band bandwidth SMU for FPGA chassis

  I'm specing on material for an FPGA FlexRIO system. The module FPGA and adapter, we will use has already been defined, a 7975R and a 5782. For our application, we will be streaming 2 inputs analog on a RT controller attached. From my understanding, these samples will be single precision floating point numbers, each of which is a piece of 4 bytes. Assuming that the 5782 max sampling rate is used, 250 MECH. / s, I think that I will need 2 GB/s of bandwidth on my SMU chassis.

  Here my question, then, what SMU chassis should I consider? The SMU-1082 has "up to 2 GB/s per-slot dedicated bandwidth", but it is a real or theoretical number? Normally, I would just get the next thing that high, just to be sure, but there is a significant price difference on the way to the SMU 1085, which is also much larger I need. So I would like to save space and several thousands of dollars if I could get away with a 1082. Sampling does not quite to the max modules of adaptation would be acceptable, but I would be interested to know where about my maximum sampling speed would be.

  Thanks in advance for your help.

  The 1082 has more than enough bandwidth to stream data at a time to the analog inputs of a 5782.  The 5782 has a 14 bit ADC with two channels that sample to 250 ms/s. These samples are returned as an I16 with the two least significant bits filled with zeros.

  So assuming that you transfer all I16, rather than packing the 14 bits of data, you would have the following bandwidth requirements.

  2 channels x 2 bytes/sample x 250 mega-samples per second = 1 GB/s

  The 1082 a 2 GB/s of throughput dedicated per slot. The 7975 accommodates up to 1.6 Gbps streaming. I would recommend calling chat with someone, if you are looking for a recommendation on what type of chassis to purchase, but based on the requirements of streaming that you're fine with the combo 7975 and 1082, you thought. Just make sure you get a controller which can accommodate streaming speeds you're looking for. The 8840 is a good candidate.

• 5154 digitizer for fpga data

  I am trying to stream as quickly as possible from the to a FlexRIO 7966 5154 digitizer.  From the example "NISCOPE fetch Forever" in LV2012, I can implement the acquisition on 5154 @ 40MS/s, 50 k of data I8 piece and the graphical indicator seems to keep well indefinitely.

  I tried then write data to an FPGA - FIFO target host, and it chokes.  With FIFO write the method inside the loop of 5154 fetch the 5154 ends in error because of the "overwhelming memory" (it fills its on-board memory until the HOST is reading).   With FIFO writing in a parallel consumer (queue conduit) loop, the queue overflows just because he can't write that as fast as the 5154 FIFO provides samples in the queue.   What Miss me?  The 5154 uses a PCI DMA bus (I think), so I think that if he could hold, the host to the FPGA PCIe bus must be capable.

  There is another factor, that I have not taken into account?   Sorry I can't provide the VI since the installation of the LV is on a PC not connected to the network.  Any advice or suggestions would be appreciated.

  Thank you

  Mark Taylor

  For future reference, I ended up resolving this by moving the implementation on the actual FPGA.   I had run in mode "on the development computer with i/o simulated" and no matter what I did with the start-up or sizing FIFO sequence, it just doesn't work.

  After compiling and running on the FPGA, all right.  Maybe it's the basic knowledge, in fact I remember somewhere in my travels reading that don't accurately represent timing problems when running to the old fashion, but LV FPGA has kind of us painted into a corner with the compromise of simulation/compilation.  They do not include Modelsim, which is the only tool that enables co-simulation do functional and verification of the timing set (we Questa, unfortunately) and independent VHDL simulation captures the interaction host with precision (and software processing/timing is impossible to quantify!).  In my situation, the only way to operate at speed is in the FPGA, but then I can't see all of the things that I need to see to debug... ARGH!

  Additional links and resources always will welcome (on debugging of FPGA LV and design in general).  I found a couple of things below, which was somewhat useful:

  "NEITHER powerful LabVIEW FPGA Developer's Guide"

  http://www.NI.com/Tutorial/14600/en/

  I found a link to an "FPGA Debug Reference Library": http://www.ni.com/example/31067/en/, but my installation does not seem to have this available.

  And it looks like 2013 may add functionality to help alleviate some of this via the node of the execution of office referred here to the 'Test and debug LabVIEW FPGA Code'

  http://www.NI.com/Tutorial/51862/en/

• Audio dropouts in streaming for magical flow device

  Hello

  I had a certain audio hang ups today.

  Check the journal of Unix, what is happening:

  26/05/2016 15:06:29.889 configd [52]: network modified: v4 (en0:192.168.0.4, en3 +:192.168.0.2) DNS * Proxy SMB

  to, I think, the same time as the break in the game.

  Has anyone else seen elsewhere? He is not related to hiring, occurs during playback of MP3 and FLAC.

  Looks like a problem with the network for me, however.

  I use an Airport express to keep WiFi (faster flow network).

  First of all, you did recently updated on your Mac or the AirPort Express? You use a VPN connection to the streaming source? Using Back to My Mac? Since you play files FLAC, I assume that you do not use iTunes as the audio server... correct?

  I recommend that you start troubleshooting cela by disabling the DNS cache on your MacBook Air with this command in Terminal:

  sudo dscacheutil-flushcache. sudo killall - HUP mDNSResponder

• The initialization of the lut for FPGA

  I am currently generate a waveform on an FPGA using a program to initialize a look-up Table (LUT).  When I select call VI of initialization, and then select the path and click OK, Labview begins to consume a lot of time CPU, but nothing seems to happen--none of the buttons except the open dialog box file and the close icon (red box with an x in the upper right corner) is grayed out.  Someone at - it ideas?  Maybe I'm doing something wrong, but there is very little documentation on this function.  I have attached the VI that I use to try to initialize my table.

  Any thoughts would be great.

  Cheers, Matt

  This must have something to do with the complexity of the LUT VI initialization.  As a work around, I simply wrote the data in a file that I then read for the initialization of LUT.  I have attached the screws again.

  The lack of reactivity is a problem, but also the absence of any indication of an error.

• Write for FPGA Boolean control RT... He switch or lock?

  I have a reset button in my FPGA code that I am trying the RT. Once this button has been programmed, do I need to "pop" back out when the FPGA reads it? The switch/latch function parameters make a difference? If I put it to lock, it will manage the return false, once it is read, for me?

  There is no lock. I think if there was, it would be much easier application handshaking with Boolean values.

• Limited to 127 for FPGA PID gain

  Hello

  I have tow questionq the first technical is the second commercial is.

  1 * for an FPGA with PXI8108 and PXI-7841R application I want to insert a value of "2100" so greater than 127, but module of pid gain is limited to 127.

  How can I do. Thanks for your help :/

  2 * I want to buy another product like target FPGA PXI-8108 for other applications, but I need PXI7841R with LABVIEW FPGA and RT I only move forward without other complementary modules to insert. Is the chassis necessary?

  I can't find other versions like PXI7841R do the same job with the same performance with PC but cheaper (no chassis & PXI-8108)? i ' am, search the Web, OR, but I have not found so can you offer me any product desired OR

  Thanks for all your response.

  Riadh WILSON.

  (2) the chassis has the RT controller. You can get cards to USB (no RT) R series FPGA / PCI / PCI-Express that plug into an ordinary PC. You can install LabVIEW Real-time on a PC, but it requires some hardware configurations so that it can be supported. Have you considered a device of RIO as a CompactRIO / sbRIO? These are materials NI Compact integrated a RT and FPGA which are cheaper than the PXI controller.

• How can I disable the firewall of windows for FPGA

  I tried to compile an FPGA vi. Towards the end of compilation, asked me if I wanted to disable something in the windows firewall (probably to allow for communication between my computer and my PXI-7854R). At the time, I had no administrative privilege and couldn't do anything but cancel this request. Of course, nothing that I compiles now runs. How to get back to the point where I can disable the firewall?

  A picture of the error message is attached.

  

  Thank you

  Stephen

  Hello Stephen,

  Thank you for posting what solved your problem - it helps other users who stumble on this troubleshooting page.  So that they can see what position fixed, could you please go ahead and mark the message as a "solution" and give good Bravo?

  Thank you!!

• Use of LABVIEW for FPGAS

  LabVIEW community support, we need your help.

  We found this question on a discussion of embedded design forum. A verilog programmer plans to LabVIEW FPGA to update his project.  We feel that his question perhaps justify a wide discussion of real users of LV FPGA so that we have here on our forum and created this thread. There the LabVIEW programmers who could offer some advice? See the question below.

  Yours truly,

  The media NOR social team

  

  Welcome to the community of LabVIEW FPGA. We will need more information about your project needs specific to suggest the current material, but in general, NOR has a wide variety of reconfigurable hardware to choose from. LabVIEW FPGA can also target several academic councils of the Xilinx University program.

  LabVIEW FPGA does not support Verilog directly as a top-level for the import file. However, if you wrap the verilog in a thin fascade VHDL, it will work since Xilinx knows how synthesize/simulate mixed models.

• execution for FPGA parallel code problem

  Hello

  I have a problem with the execution of the code in parallel on the FPGA to a cRIO-9073.
  Running the code takes more time than expected.
  The problem is described in the attached PDF file.

  Kind regards

  Beurms Jasper

  Hi Jasper,.

  the first problem is due to DATA streams! THINK THE STREAM!

  You have three simultaneous sequences. The loop iteration time depends on the slowest component in the loop. If you don't need to ask why the 'low frequency sequence' minimalist other sequences?

  The 2nd problem cannot be discussed looking at the pictures. What are those who wait function? milliseconds, microseconds, ticks?

  Did you know that the IO nodes also take some time to treatment?

• How to transfer a single RT for FPGA data

  I start working with the CRio-9012, I want to know how to transfer data from the FPGA RT, I found something about DMA FIFOS, however I notice that it is only possible to transfer pictures, I don't know if I'm doing something wrong. I have another question, is it possible global variable usage in the data transfers between RT and FPGA?

  Filipe

  280584 wrote:
  If I try a fifo DMA allows you to transfer data between FPGA and RT, I choose TYPE: ok DMA HOST-TARGET? or SCOPE TARGET must be selected? In this case, my host is the RT and the target is FPGA ok?

  Yes, you will need to use 'Host to Target' or 'Target to Host' (the FPGA is the target, RT is the host); the one who depends on the direction that where you want to send the data.  Target range is for FIFO that is used only on the FPGA. they are useful for transferring data between the simultaneous loops in FPGA code.

• The drive mapped to the directory of Streaming for WSM?

  My original WSM server is 6.0 on a virtual computer to Win7.  Streaming directory is on a virtual hard disk in the same VM.

  For my next step, I took this virtual hard disk and shared on the network.

  I'm testing vWorkspace 7.2 on a Win 2 k 8 R2 VM.  I installed 7.2 WSM very well, but I tried to use the newly shared disk of my WSM original server to have access to the images continuously on the server of 7.2.  I get an error: "Streaming directory is not always accessible. Please check access authorization / availability. »

  I tested access the folder via the general browsing through Explorer, power without problem.  My feeling is that WSM might have a problem with the store being on a shared network drive.

  Know a solution or give me a hint to make this work?  I try to avoid having to configure a virtual hard disk duplicate on the SAN, which is short on space.

  Thank you!

  Hello Eric,

  sharing a picture of system operating between the separate facilities of WSM is not supported. If you could patch the Image on a single system, the other server does not know about it and can run in incalculable stakes.

  If the StreamingDir is located on a network share, the WSM Server Services must be running with the privileges of a full user with read/write permissions to the share. I recommend using Service WSM references to that effect.

  Planning and design of WSM guide covers this on page 25.

  I hope this helps!

• Video stream (for example a film) that is stored on my laptop to my TV please (as they do on windws 7 adds)?

  I have a Sony Vaio laptop running windows 7 and a smart TV Sony Bravia, that both are connected to the wireless internet. Can you tell me how I stream video (say a movie) that is stored on my laptop to my TV, please (as they do on windws 7 adds)?

  There is an option for televisions that will allow you to do wireless.  I believe it is called WIDI.  I saw it advertised, but have no experience with it.  You should be able to find out about the places that sell TVs for more information.

  Good luck.

• Need information about dataguard / stream for our scenerio!

  Hello
  
  We have an application with Oracle 11 g (he calls as box 1), the day-to-day operations of form currently apart load that we have, there are two or three other apps also considered tapping/approach of our primary database (box 1) that puts a lot of load on the Pb and the server. I've done a few go - ogle and found that data guard or water courses can come handy also to lower the load through box 2 dB pending... So I think I have a standby server either box 2 that will meet all reporting requirements and primary will just play a role of data entry & req little statement.
  
  So my question to you guys is:
  
  (1) assuming I want to just unload some server load in box 2 in effect considered, is an option to fetch DataGuard. If Yes, then what I have to go with physical or logical standby standby assuming that our database awaiting will be just right for having reported the end or in other words all the reports of applications such as data warehouse wil approaching standby db?
  
  2) given that I understood the watercourse is very convenient if I want to have more control over what is shipped in box 2 as an update, as you much finer granule setting i.e. level table, etc. level collar. Since we have always have full db in sync, stream be not useful in our case, the right?
  
  
  -Learner

  Hello

  Here, two things are different) 1 standby) 2 flow, obviously related to replication

  From 11 g, you can use physical standby for payment purposes, this means select statements will work i.e. you can say read-only data recovery also will be activated too.

  In this process, users who perform operations only in read-only , no operation of inserts/updates / removal is permitted.

  In streams, it works on heterogeneous platforms, you can perform the data replication, which can be also some objects or diagram, complete database. There will be a lot of addiction too.

  To SYNCHRONIZE the two databases that you can fetch the data keep that only comes with the cost of the Enterprise edition. Mode standby is exactly the mirror copy.

  HTH