Specifications of time contradictory of NAT9914

It seems to be conflicting information between the 2 documents the details of diagram of timing for processor-to-9914 communication for a parallel interface (reading and writing). I would like to know which of the 2 documents has the correct information to be used for correct communication for the NAT9914. 2 documents are:

IEEE 488.2 controller chip, 372013 B-01, Sep06

Application Note 110, design of a device GPIB using the NAT9914, 341398 A-0, January 1998

Thank you

Sailing,

I'm looking for in this gap.  Right now, I would recommend looking at the specification NAT9914 IEEE 488.2 controller chip as your reference, given that the application note is older and has been removed from our Web site.

I'll post here when I confirmed the specifications of good timing.

Tags: NI Hardware

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