LabVIEW FPGA: Deploy fpga with host program

Similar Questions

• Simulate the sine wave using LabVIEW FPGA with NOR-myRIO and display in real time

  Hello

  I'm relatively new to LabVIEW FPGA. I am trying to test (and later apply) controllers high speed on myRIO.

  At this point, I'm trying to simulate the sine wave from 1 to 10 kHz using Sinewave generator VI express. I also intend to display the sine wave on the time real (RT) using FIFO. However, I had a bit of trouble to understaing various synchronization parameters.

  1. how to encode information about the sampling frequency generating sine wave? (The side FPGA vi requires only the frequency of the signal and possibly phase and does not rate update lines)

  2. how to estimate the number of items in a FIFO? (that is, the relationship between the rate of updates to loop (RT), the signal frequency, sampling frequency and the number of items in the FIFO)

  It would be great if we could share a very simple program (side host and target) that did something similar.

  Thank you

  MILIN

  Milot,

  I think the problem is the type of data in your FIFO. Your FIFO is configured to use a data type of I16. The problem is the number, it displays only ever will be-1, 0 or 1. To resolve this problem, you must send the sine wave as a fixed point data and convert it to a double on the side of the RT. This should significantly improve your resolution.

• Acquiring temp with NI 9214 using labview fpga

  Hello

  I'm a student, very new to labview and data acquisition. I had problems with a thermocouple type T of wiring to a NI 9214 module and writing a program labview FPGA to acquire temperatures. I've been struggling with this and for a long time to research on the web without success.

  Please find attached the code that I work with. I was told to use the value obtained from the CJC and converted using the formula I found here ( http://zone.ni.com/reference/en-XX/help/370984T-01/criodevicehelp/9214_converting/ ) and arrays of conductor thermocouple type T to find the temperature, but I didn't get anything that makes sense.

  Please can someone help me?

  Jeremiah

  Hi Jeremiah,.

  You use this 9214 in cRIO chassis? If Yes, which model?

  Regarding the conversion of the data, you have to take care to recover the data from the side host (you'll need a separate VI) and taking care of converting it. When you mention that you don't get what makes sense, what exactly read / do you expect?

  I strongly suggest you open and tinkering with the example of the host/FPGA shipping screw to the 9214 (NI 9214 Get Started.lvproj, found in the program NIUninstaller Instruments\LabVIEW 2013\examples\CompactRIO\Module Specific\NI 9214\NI 9214 Getting Started). It should allow you to have a good knowledge in understanding the relationship between the host and the screw of the FPGA.

  I hope this helps!

• A UDP connection target FPGA with LabVIEW

  Hello

  I have an FPGA with Ethernet connected to my HOST PC, now I would like to connect the LabVIEW FPGA target and access to its records. Please suggest me.

  Kind regards

  Chetan

  Hi Cheetah,.

  don't know, because I do not know your format or the manual of your FPGA...

• LabVIEW FPGA failure with compiler Xlinx?

  I'm in LabVIEW FPGA 8.6 with NOR-RIO 3.0.1 (to 8.6).  When I compile a simple program, I get the notorious:

  «Error starting compile step: make sure that a compatible version of Xilinx tools is installed in the location specified in the setup of LabVIEW FPGA.»

  I checked the FPGA compile server and I ran the utility fixTlink.VI with no improvement.  This produces two identical PC, neither one having a FPGA installed card.

  Any ideas?

  After further analysis, the problem was to be in our facility in LabVIEW FPGA 8.6.   Using the correct Installer of NEITHER solved the problem.

  This thread is now resolved.

• The project-centric issue of peer to Peer with an external compiler in LabVIEW FPGA

  Hi all

  FPGA OR Version: 14.0

  I have an application developed in LabVIEW interfacing FPGAs developed in LabVIEW FPGA making of peer to peer Communications.

  Everything works fine.

  I try on the port to Visual Studio 2013 (on the same PC) and am able to communicate with the FPGA very well using the C API.

  However, I have a problem now with the help files or the peer supported external compiler peer.

  I get these errors:

  1. cannot open the file source 'PublicIncludes/nistreamCommon/prefix.h '.

  2. impossible opening the file source 'PublicIncludes/nistreamCommon/postfix.h '.

  in

  c:\Program Files (x 86) \National Instruments\Shared\ExternalCompilerSupport\C\include\nip2p.h

  in my project...

  I looked in the folder c:\Program Files (x 86) \National Instruments\Shared\ExternalCompilerSupport\C\include\ and the PublicIncludes\nistreamCommon folder does not exist.

  What I am doing wrong?

  Hello!

  It seems that you have worked with another engineer of Applications on this issue.  For the love of documents, the nip2p library is not supported in CVI. There has been cases where users were able to get this work to comment on the two header files.

  Thank you!

• Software FPGA with LabVIEW 2013

  I have a system with a rotating computer "development" under Windows 7 and an NI PXI-1036 chassis with a PXI-8101 controller as well as a card FPGA PXI-7853R. Recently, I upgraded to LabVIEW 2011-2013 of LabVIEW. I kept LabVIEW 2011 installed just to make sure everything is still working on the new LabVIEW.

  Now, when I open my project in LabVIEW 2013 Project Explorer, my FPGA comes with a warning triangle yellow next to him (see attached photo). The warning says:

  "Software support for this target FPGA is not installed on the computer. You can view and copy elements into the project, but you can not compile any screw under the FPGA target, until you install support for the target. Refer to the documentation of specific material for more information on the proper drivers and for more information about the installation and configuration of the target FPGA ".

  Regarding the installed software, I have LabVIEW SP1 of 2013, 2013 of LabVIEW FPGA Module SP1, SP1 of Module 2013 LabVIEW Real-time, and Xilinx Compilation tools 14.4. On the chassis of the TARGET (with the PXI-8101 controller), I have attached a list of installed software.

  Interestingly, when I open the project in LabView 2011, no errors or warnings are present with the FPGA card. It is only under LabVIEW 2013 I see the warning. Did anyone see a glaring omission of software that could be the cause of LabVIEW raise this error? Thank you for your help.

  

  

  Best guess is that're missing you the driver for your FPGA device. Try to install the latest version of NOR-RIO (or at least the version supplied on your 2013 SP1 install disks). Have you installed device drivers at the time that you have installed SP1 2013 LabVIEW?

• NEITHER 9512 with Labview FPGA Interface

  Is it possible to use the NI 9512 stepper with Labview FPGA interface drive unit or is it only possible to use it with the interface of scanning? When I try to add the module to a FPGA target, I get an error telling me that Labview FPGA does not support this module with the latest version of NOR-RIO, but I have the latest version of OR-installed RIO.

  Hi Checkit,

  You're right - the 9512 cannot currently be used in FPGA. There is an error in the documentation. The 9514 and 9516 can, however.

• Model a block synchronous dual-port RAM with LabVIEW FPGA

  This question caught my attention recently.

  I am trying to model a particular design element called "RAMB4_S8_S8" with the LabVIEW FPGA module. This element is a block synchronous dual-port RAM allowing simultaneous access to two ports independently from each other. That being said, a port can perform read/write operation to this RAM while at the same time, the other port might be able to do the same thing. There are two opportunities of possible port conflict, however. The first is when both ports are trying to write to the same memory cell. The other scenario is when a port writes in a cell memory while at the same time the other port reads from it. Other than that, everything should be a legitimate operation.

  In order to reproduce this I select memory block that is integrated into my FPGA target. An interface is configured to be the playback mode, and the other is set to write fashion. For the option of arbitration, I let the two interfaces to be "arbitrate if several applicants only. Then I got a compiler error when I tried to run my FPGA code for this model in a SCTL. The error message is something like "several objects to request access to a resource through a resource configured with option interface" arbitrate if several applicants only ", which is supported only in the single-cycle Timed loop if there is only a single applicant by interface.

  This error goes away if I replace the SCTL with a simple while loop, but not what I would like to implement. So I wonder if there is a better solution to this problem, or is it just the limitation of the LabVIEW FPGA module.

  Thank you.

  Yes, you can use a form of conduct to perform the operations you want in the generations clock cycles, but all the code is inside a single SCTL. Basically, read the first address and storing in a register in a single cycle and then read the second address in the second clock cycle. This would allow you to two readings of valid memory every clock cycle 2. I have included a crude extract to illustrate the concept. The case selectors are identical with address A being connected to the memory in the true case, B in the case of fake address. Your biggest model memory dual port will be intact, but it will operate at 1/2 rate.

  Take a look at the white paper that provides more details on the construction of memory:

  Data on a target FPGAS (FPGA Module)

  The ball on the memory block indicates that memory block double port cannot be applied in a configuration of reading, which is a double ROM. access read/write port must be imitated with custom code.

• HELP - FPGA SPARTAN 3E-100 CP132 WORKS WITH LABVIEW FPGA?

  HI EVERYONE, GET ON IM TRYING TO USE MY FPGA WITH LABVIEW, BUT I DO KNOW THAT IF ITS COMPATIBLE, I INSTALLED THE DRIVERS, MODULE FPGA AND LABVIEW 2012, IM USING WINDOWS 7 32 BIT, AND AFTER I COMPILED ITS SAYS:

  LabVIEW FPGA called another software component, and the component returned the following error:

  Error code:-310601

  NOR-COBS: Impossible to detect the communication cable.
  Check the communication cable is plugged into your computer and your target. Also, verify that the proper drivers are installed.

  Thank you.

  =)

  Hi dvaldez2.

  LabVIEW FPGA offers no support for any material to third parties, other than the 3rd Spartan XUP Starter Kit. These are probably the drivers you downloaded.

  http://digital.NI.com/express.nsf/bycode/Spartan3E?OpenDocument&lang=en&node=seminar_US

  However, this driver supports only the Starter Kit Board itself (http://www.digilentinc.com/Products/Detail.cfm?NavPath=2, 400, 790 & Prod = S3EBOARD). You may not use the driver with any other Xilinx FPGAS.

  I hope this helps.

• problems with the project of example LabVIEW FPGA

  I'm trying to adapt the example project record on CompactRIO and LabVIEW FPGA Waveform Acquisition for my hardware, but can't seem to do things. I'm just following the instructions in the tutorial, but can not make sense out of section adapt this example to your hardware project, in particular, the instruction to "Drag FPGA Main.vi in the Project Explorer in the Open FPGA VI service window reference VI." Can someone explain on what is supposed to happen here? BTW, the target hardware that I'm doing this work on is a cRIO-9068 with some C series i/o modules.

  Finally, I came across the answer. For anyone else who may encounter this problem, the attached screenshot is worth a thousand words.

• Exactly how memory works in Labview Fpga

  I use a PXI 7853 and me for the last few days I've been playing with the help of blocks of memory in the FPGA.

  Now, I'm relatively new to Labview FPGA programming and this is why I would be grateful if someone could provide me with some clarification on the following points:

  (a) given that I work on the development host computer when I initialize memory with the ability to use a memory initialization VI then how does exactly in the backend. What I want to ask is, when I change the values of the memory in the computer development and then compile the FPGA VI in the Board of Directors, what is data memory are brought in the FPGA. If this is the case then in what form are the details initially registered in the development computer.

  (b) is it possible for me to use the initialization method VI to change memory n valuesi while the FPGA VI is running. If this isn't the case, then it would make a difference if I stop the VI and then change the values using the Initialize method. Who would actually reflect on the FPGA or should I have to re compile the FPGA VI whenever I change memory values in the development machine, using the "VI initialization method (which is available as an option for us do a right-click on the block of memory in the Project Explorer window).

  I tried test with simulation of FPGA VI and found that when I try to change the values of memory by running VI initialization. a pop up that says that it is not possible that the FPGA VI is still in service is delivered.

  Any light on this or advice with links would be much appreciated

  See you soon

  sbkr

  sbkr wrote:

  (a) given that I work on the development host computer when I initialize memory with the ability to use a memory initialization VI then how does exactly in the backend. What I want to ask is, when I change the values of the memory in the computer development and then compile the FPGA VI in the Board of Directors, what is data memory are brought in the FPGA. If this is the case then in what form are the details initially registered in the development computer.

  When you compile the FPGA VI, he will understand the values used to initialize the memory.

  Are asking you what happens if you run the VI FPGA on your development computer, and your FPGA VI, written in the memory block, the new values are included when you compile the FPGA VI? No, these values will be lost. The values contained in the bitfile are the values you used to initialize the block of memory, as defined in the memory properties dialog box. The initial values are saved in the LabVIEW project file and the definition of memory block.

  sbkr wrote:

  (b) is it possible for me to use the initialization method VI to change memory n valuesi while the FPGA VI is running. If this isn't the case, then it would make a difference if I stop the VI and then change the values using the Initialize method. Who would actually reflect on the FPGA or should I have to re compile the FPGA VI whenever I change memory values in the development machine, using the "VI initialization method (which is available as an option for us do a right-click on the block of memory in the Project Explorer window).

  You will have to recompile the FPGA in order to use the new initialization values, because these values are part of the bitfile FPGA.

• LabVIEW FPGA SP1 2012 & EVS1464RT FPGA IO

  Hello

  There seems to be problems with the new Labview FPGA 2012 SP1 in combination with an EVS1464RT embedded Vision system, which took place only after upgrading to SP1 2012 Labview:

  • While trying to compile our code for the EVS1464RT FPGA or (Vision system embedded with e/s based on a FPGA Virtex-II FPGA) Xilinx tools (V10.1, since it's a Virtex-II FPGA) has reported an error saying that the compilation work has tried to set the property 'Data (output events)', which does not exist, so the Xilinx tools just quit with an error.

    A complete uninstall and reinstall 'clean' do not solve the problem.

    Research has shown that there is a property correct for Xilinx tools, called "done (output events)." An extended search in the Labview upwards 'incorrect data (output events)' some text files in 2 files "resource.xml" in the directories '...\National Instruments\LabVIEW 2012\Targets\NI\FPGA\IMAQIO\IMAQIO-1 "and '...\National Instruments\LabVIEW 2012\Targets\NI\FPGA\IMAQIO\IMAQIO-5' (and nowhere else).". " Change these 2 texts to 'Done (output events)' corrected the error and allowed to compile the code again.

  • Another problem is that you can not start the VI FPGA-interactive (for example by clicking the Run button). This product just another error message saying that the VI '...\National Instruments\LabVIEW 2012\vi.lib\FPGAPlugInAG\IMAQIO-5\niFpgaOpenAndRun_IMAQIO-5.vi' could not be found (and there really is not anywhere on the hard drive).

    The FPGA VI can be started from an another VI on the target host by using the function "Reference open FPGA". Then it works without any problems, so the bitfile has been obviously compiled correctly.

  All of this worked out of the box without any problems on my old installation of Labview (before 2012 SP1 update).

  The first problems now seems to be a simple typo, and using the function "Open FPGA reference" is a workaround for the second problem. But I'm very angry that National Instruments does not seem to test their software before releasing. A service pack should never break things that worked before.

  Find these alternatives cost me 3 days, which, in my opinion, could be acceptable for open-source software, but not if you pay hundreds of euros per year for a "Standard Service program. For that kind of money, I expected NOT to test all the changes that they do well.

  Best regards

  Dr. Merlin Welker

  Hello Mr. Welker.

  First of all, thank you for your comments. I'm really sorry that you stumbled on this issue. Please let me give you some background information on it.

  You are right that the update for the versions of service pack is to address reported problems and he should never break things that worked before. Unforunately, a change in LabVIEW FPGA exposed an underlying issue with e/s NOR-IMAQ driver FPGA compilation. We have identified this issue and addressed it in the Acquisition of Vision Software communicated in February 2013, including e/s NOR-IMAQ 2.6.1.

  It is now available in the Update Service of NOR. We also found and addressed the issue with the FPGA Open running and run interactively in the thatsame release.

  We recommend the upgrade to use the latest version of driver, whenever you upgrade from versions of LabVIEW, to ensure better compatibility between them. Please note that whenever you upgrade LabVIEW FPGA or Vision Acquisition Software, you should also recompile your LabVIEW FPGA projects.

  While these issues were found and corrected in the latest version, we are now reminded our development and testing processes for future versions. Please accept our apologies for the inconvenience. National Instruments is committed to your satisfaction and to maintain your confidence in our products.

  Thank you

  Elmar

• LabVIEW FPGA, 2015 compilation error

  I've recently switched to LabVIEW 2015 and I'm working on OR myRIO. So also installed myRIO 2015 bundled software. The problem I have is that the compilation of fpga fails within 10 seconds.

  

  and the target Xilinx journal report is empty

  

  The first time when I tried to compile on 2015 version, it failed and the message box that failed came alongwith the avast antivirus warning for malicious activity. I reported it as wrong and now I tried several times with avast shield disabled control, but the results are the same. While the version of labVIEW 2014 works very well.

  Now, I'm sure that there is something wrong with the installation of Vivado because this dll is part of it. The dll must be default in the2014_4\lib\win32.o directory C:\NIFPGA\programs\Vivado if you are using an operating system for 32-bit AND also in C:\NIFPGA\programs\Vivado2014_4\lib\win64.o If you use a 64-bit operating system. If the dll is not here, it is probably that the anti virus (I've never seen what happens to Xilinx but I have for other stuff).

  I'm emphasizing the 2014_4 because LabVIEW 2015 uses Vivado 2014_4 while 2014 LabVIEW uses Vivado 2013_4. Since you have also installed LabVIEW 2014, you must have 2013_4 as well and if it works, you will find the dll I just wanted you make sure you check the correct directory for the Vivado 2014_4.

  Download and install (reinstall or repair if already installed) 2015 LabVIEW FPGA Module Xilinx tools Vivado 2014.4. You can also use the DVD Setup if you have. It would be a good idea to do the installation with the disabled and even anti-virus try the first compilation the same. Try and let me know if the problem persists.

  Kind regards

• Internal software error of LabVIEW FPGA Module - 61499

  I get the error next (in a pop-up window) in the phase of sompilation for the FPGA target with a vhdl IP. This error continues to occur even after restart LabVIEW and the PC. Someone at - it solved is this kind of problem before without having to re - install the software?

  Here is the error information:

  Error-61499 occurred at niFpgaXml_GetValue_String.vi<><><><>

  Possible reasons:

  LabVIEW FPGA: An internal software error in the LabVIEW FPGA Module has occurred. Please contact National Instruments technical support on ni.com/support.

  Additional information: lack the tag required XML (/ CompileServerList)

  As a first step, I can compile the vhdl IP node successfully. However, once when I'm running a VI with the FPGA, the bureau stop working. After that I restarted by force, it cannot perform the build of a vhdl IP node. Even without connecing to the jury of LabView, he pointed out errors before the end of the sompilation.

  Interestingly, the screw which also includes nodes IP vhdl that I properly compiled before, I can still run the VI to the Commission and it works correctly.

  Thank you

  Looks like your ActiveJobsList somehow has been corrupted. I saw occur when computers are hard stop or blue screen during compilation. I don't have that LabVIEW 2014 installed on my machine, so your path will be a little different, and the file extension will be a .txt or .xml instead of .json, but try this:

  Move the file "C:\Program Files (x 86) \National Instruments\LabVIEW 2014\vi.lib\rvi\CDR\niFpgaActiveJobList.json" (or your equivalent) out of the above directory (back it upward and delete essentially) and restart LabVIEW. Must regenerate the file and resolve the problem.